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Register a new userSub-micrometer epitaxial Josephson junctions for quantum circuits
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We present a fabrication scheme and testing results for epitaxial sub-micrometer Josephson junctions. The junctions are made using a high-temperature (1170 K) via process yielding junctions as small as 0.8 mu m in diameter by use of optical lithography. Sapphire (Al2O3) tunnel-barriers are grown on an epitaxial Re/Ti multilayer base-electrode. We have fabricated devices with both Re and Al top electrodes. While room-temperature (295 K) resistance versus area data are favorable for both types of top electrodes, the low-temperature (50 mK) data show that junctions with the Al top electrode have a much higher subgap resistance. The microwave loss properties of the junctions have been measured by use of superconducting Josephson junction qubits. The results show that high subgap resistance correlates to improved qubit performance.
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For high-performance superconducting quantum devices based on Josephson junctions (JJs) decreasing lateral sizes is of great importance. Fabrication of sub-mu m JJs is challenging due to non-flat surfaces with step heights of up to several 100 nm generated during the fabrication process. We have refined a fabrication process with significantly decreased film thicknesses, resulting in almost flat surfaces at intermediate steps during the JJ definition. In combination with a mix-&-match process, combining electron-beam lithography (EBL) and conventional photolithography, we can fabricate JJs with lateral dimensions down to 0.023 mu m^2. We propose this refined process as an alternative to the commonly used chemical-mechanical polishing (CMP) procedure. We present transport measurements of JJs at 4.2 K that yield critical-current densities in the range from 50 to 10^4 A/cm^2. Our JJ process yields excellent quality parameters, Rsg/Rn up to ~50 and Vgap up to 2.81 mV, and also allows the fabrication of high-quality sub-mu m wide long JJs (LJJs) for the study of Josephson vortex behavior. The developed technique can also be used for similar multilayer processes and is very promising for fabricating sub-mu m JJs for quantum devices such as SQUIDs, qubits and SIS mixers.
Magnetic flux quantization in superconductors allows the implementation of fast and energy-efficient digital superconducting circuits. However, the information representation in magnetic flux severely limits their functional density presenting a long-standing problem. Here we introduce a concept of superconducting digital circuits that do not utilize magnetic flux and have no inductors. We argue that neither the use of geometrical nor kinetic inductance is promising for the deep scaling of superconducting circuits. The key idea of our approach is the utilization of bistable Josephson junctions allowing the representation of information in their Josephson energy. Since the proposed circuits are composed of Josephson junctions only, they can be called all-Josephson junction (all-JJ) circuits. We present a methodology for the design of the circuits consisting of conventional and bistable junctions. We analyze the principles of the circuit functioning, ranging from simple logic cells and ending with an 8-bit parallel adder. The utilization of bistable junctions in the all-JJ circuits is promising in the aspects of simplification of schematics and the decrease of the JJ count leading to space-efficiency.
We have studied fundamental properties of weak-link Sr2RuO4/Sr2RuO4 Josephson junctions fabricated by making a narrow constriction on superconducting Sr2RuO4 films through laser micro-patterning. The junctions show a typical overdamped behavior with much higher critical current density, compared with those previously reported for bulk Sr2RuO4/s-wave superconductor junctions. Observed magnetic field and temperature dependences of the Josephson critical current suggest that the chiral p-wave is unlikely for the superconducting symmetry, encouraging further theoretical calculations of the Sr2RuO4/Sr2RuO4 type junctions.
We combine electron beam lithography and masked anodization of epitaxial aluminium to define tunnel junctions via selective oxidation, alleviating the need for wet-etch processing or direct deposition of dielectric materials. Applying this technique to define Josephson junctions in proximity induced superconducting Al-InAs heterostructures, we observe multiple Andreev reflections in transport experiments, indicative of a high quality junction. We further compare the mobility and density of Hall-bars defined via wet etching and anodization. These results may find utility in uncovering new fabrication approaches to junction-based qubit platforms.
New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stoplayers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (Ic) targeting and reproducibility, eliminate aging, and eliminate pattern-dependent effects in Ic and tunneling characteristics of Nb/Al/AlOx/Nb junctions in integrated circuits. The latter effects were recently found in Nb-based JJs integrated into multilayered digital circuits. E.g., it was found that Josephson critical current density (Jc) may depend on the JJs environment, on the type and size of metal layers making contact to niobium base (BE) and counter electrodes (CE) of the junction, and also change with time. Such Jc variations within a circuit reduce circuit performance and yield, and restrict integration scale. This variability of JJs is explained as caused by hydrogen contamination of Nb layers during wafer processing, which changes the height and structural properties of AlOx tunnel barrier. Redistribution of hydrogen impurities between JJ electrodes and other circuit layers by diffusion along Nb wires and through contacts between layers causes long-term drift of Jc. At least two DSLs are required to completely protect JJs from impurity diffusion effects - right below the junction BE and right above the junction CE. The simplest and the most technologically convenient DSLs we have found are thin (from 3 nm to 10 nm) layers of Al. They were deposited in-situ under the BE layer, thus forming an Al/Nb/Al/AlOx/Nb penta-layer, and under the first wiring layer to junctions CE, thus forming an Al/Nb wiring bi-layer. A significant improvement of Jc uniformity on 150-mm wafer has also been obtained along with large improvements in Jc targeting and run-to-run reproducibility.
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