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This paper contains a compilation of parameters influencing the charge collection process extracted from a comprehensive study of partially depleted Monolithic Active Pixel Sensors with small (<25 um$^2$) collection electrodes fabricated in the TowerJazz 180 nm CMOS process. These results gave guidance for the optimisation of the diode implemented in ALPIDE, the chip used in the second generation Inner Tracking System of ALICE, and serve as reference for future simulation studies of similar devices. The studied parameters include: reverse substrate bias, epitaxial layer thickness, charge collection electrode size and the spacing of the electrode to surrounding in-pixel electronics. The results from pixels of 28 um pitch confirm that even in partially depleted circuits, charge collection can be fast (<10 ns), and quantify the influence of the parameters onto the signal sharing and amplitudes, highlighting the importance of a correct spacing between wells and of the impact of the reverse substrate bias.
Edge-TCT and charge collection measurements with passive test structures made in LFoundry 150 nm CMOS process on p-type substrate with initial resistivity of over 3 k$Omega$cm are presented. Measurements were made before and after irradiation with re
The barrel region of the CMS pixel detector will be equipped with ``n-in-n type silicon sensors. They are processed on DOFZ material, use the moderated p-spray technique and feature a bias grid. The latter leads to a small fraction of the pixel area
High-Voltage Monolithic Active Pixel Sensors (HV-MAPS) based on the 180 nm HV-CMOS process have been proposed to realize thin, fast and highly integrated pixel sensors. The MuPix7 prototype, fabricated in the commercial AMS H18 process, features a fu
Pixel sensors using 8 CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using
We have operated a Medipix2 CMOS readout chip, with amplifying, shaping and charge discriminating front-end electronics integrated on the pixel-level, as a highly segmented direct charge collecting anode in a three-stage gas electron multiplier (Trip