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تسجيل مستخدم جديدRegional Clock Tree Generation by Abutment in Synchoros VLSI Design
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Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. Standard cells are replaced by synchoros large grain VLSI design objects called SiLago blocks. This new design style enables end-to-end automation of large scale designs by abutting the SiLago blocks to eliminate logic and physical synthesis for the end-users. A key problem in this automation process is the generation of regional clock tree. Synchoros design style requires that the clock tree should emerge by abutting its fragments. The clock tree fragments are absorbed in the SiLago blocks as a one-time engineering effort. The clock tree should not be ad-hoc, but a structured and predictable design whose cost metrics are known. Here, we present a new clock tree design that is compatible with the synchoros design style. The proposed design has been verified with static timing analysis and compared against functionally equivalent clock tree synthesised by the commercial EDA tools. The scheme is scalable and, in principle, can generate arbitrarily complex designs. In this paper, we show as a proof of concept that a regional clock tree can be created by abutment. We prove that with the help of the generated clock tree, it is possible to generate valid VLSI designs from 0.5 to ~2 million gates. The resulting generated designs do not need a separate regional clock tree synthesis. More critically, the synthesised design is correct by construction and requires no further verification. In contrast, the state-of-the-art hierarchical synthesis flow requires synthesis of the regional clock tree. Additionally, the conventional clock tree and its design needs a verification step because it lacks predictability. The results also demonstrate that the capacitance, slew and the ability to balance skew of the clock tree created by abutment is comparable to the one generated by commercial EDA tools.
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