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تسجيل مستخدم جديدOn Error-Correction Performance and Implementation of Polar Code List Decoders for 5G
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Polar codes are a class of capacity achieving error correcting codes that has been recently selected for the next generation of wireless communication standards (5G). Polar code decoding algorithms have evolved in various directions, striking different balances between error-correction performance, speed and complexity. Successive-cancellation list (SCL) and its incarnations constitute a powerful, well-studied set of algorithms, in constant improvement. At the same time, different implementation approaches provide a wide range of area occupations and latency results. 5G puts a focus on improved error-correction performance, high throughput and low power consumption: a comprehensive study considering all these metrics is currently lacking in literature. In this work, we evaluate SCL-based decoding algorithms in terms of error-correction performance and compare them to low-density parity-check (LDPC) codes. Moreover, we consider various decoder implementations, for both polar and LDPC codes, and compare their area occupation and power and energy consumption when targeting short code lengths and rates. Our work shows that among SCL-based decoders, the partitioned SCL (PSCL) provides the lowest area occupation and power consumption, whereas fast simplified SCL (Fast-SSCL) yields the lowest energy consumption. Compared to LDPC decoder architectures, different SCL implementations occupy up to 17.1x less area, dissipate up to 7.35x less power, and up to 26x less energy.
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SC-Flip (SCF) is a low-complexity polar code decoding algorithm with improved performance, and is an alternative to high-complexity (CRC)-aided SC-List (CA-SCL) decoding. However, the performance improvement of SCF is limited since it can correct up
to only one channel error ($omega=1$). Dynamic SCF (DSCF) algorithm tackles this problem by tackling multiple errors ($omega geq 1$), but it requires logarithmic and exponential computations, which make it infeasible for practical applications. In this work, we propose simplifications and approximations to make DSCF practically feasible. First, we reduce the transcendental computations of DSCF decoding to a constant approximation. Then, we show how to incorporate special node decoding techniques into DSCF algorithm, creating the Fast-DSCF decoding. Next, we reduce the search span within the special nodes to further reduce the computational complexity. Following, we describe a hardware architecture for the Fast-DSCF decoder, in which we introduce additional simplifications such as metric normalization and sorter length reduction. All the simplifications and approximations are shown to have minimal impact on the error-correction performance, and the reported Fast-DSCF decoder is the only SCF-based architecture that can correct multiple errors. The Fast-DSCF decoders synthesized using TSMC $65$nm CMOS technology can achieve a $1.25$, $1.06$ and $0.93$ Gbps throughput for $omega in {1,2,3}$, respectively. Compared to the state-of-the-art fast CA-SCL decoders with equivalent FER performance, the proposed decoders are up to $5.8times$ more area-efficient. Finally, observations at energy dissipation indicate that the Fast-DSCF is more energy-efficient than its CA-SCL-based counterparts.
This work identifies information-theoretic quantities that are closely related to the required list size for successive cancellation list (SCL) decoding to implement maximum-likelihood decoding. It also provides an approximation for these quantities
that can be computed efficiently for very long codes. There is a concentration around the mean of the logarithm of the required list size for sufficiently large block lengths. We further provide a simple method to estimate the mean via density evolution for the binary erasure channel (BEC). Simulation results for the binary-input additive white Gaussian noise channel as well as the BEC demonstrate the accuracy of the mean estimate. A modified Reed-Muller code with dynamic frozen bits performs very close to the random coding union (RCU) bound down to the block error rate of $10^{-5}$ under SCL decoding with list size $L=128$ when the block length is $N=128$. The analysis shows how to modify the design to improve the performance when a more practical list size, e.g., $L=32$, is adopted while keeping the performance with $L=128$ unchanged. For the block length of $N=512$, a design performing within $0.4$ dB from the RCU bound down to the block error rate of $10^{-6}$ under an SCL decoder with list size $L=1024$ is provided. The design is modified using the new guidelines so that the performance improves with practical list sizes, e.g., $Lin{8,32,128}$, outperforming 5G designs.
This paper presents an efficient hardware design approach for list successive cancellation (LSC) decoding of polar codes. By applying path-overlapping scheme, the l instances of (l > 1) successive cancellation (SC) decoder for LSC with list size l ca
n be cut down to only one. This results in a dramatic reduction of the hardware complexity without any decoding performance loss. We also develop novel approaches to reduce the latencyassociated with the pipeline scheme. Simulation results show that with proposed design approach the hardware efficiency is increased significantly over the recently proposed LSC decoders.
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