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This paper presents the design and analysis of a wearable CMOS biosensor with three different designs of energy-resolution scalable time-based resistance to digital converters (RDC), targeted towards either minimizing the energy/conversion step or maximizing bit-resolution. The implemented RDCs consist of a 3-stage differential ring oscillator which is current starved with the resistive sensor, a differential to single ended amplifier, an off-chip counter and serial interface. The first design RDC included the basic structure of time-based RDC and targeted low energy/conversion step. The second design RDC aimed to improve the rms jitter/phase noise of the oscillator with help of speed-up latches, to achieve higher bit-resolution as compared to the first design RDC. The third design RDC reduced the power consumption by scaling the technology with the improved phase-noise design, achieving 1-bit better resolution as that of the second design RDC. Using a time-based implementation, the RDCs exhibit energy-resolution scalablity, and consume 861nW with 18-bit resolution in design 1 in TSMC 0.35um technology. Design 2 and 3 consume 19.1uW with 20-bit resolution using TSMC 0.35um, and 17.6uW with 20-bit resolutions using TSMC 0.18um, respectively (both with 10ms read-time, repeated every second). With 30ms read-time, design 3 achieves 21-bit resolution, which is the highest resolution reported for a time-based ADC. The 0.35um time-based RDC is the lowest-power time-based ADC reported, while the 0.18um time-based RDC with speed-up latch offers the highest resolution. The active chip-area for all 3-designs are less than 1.1 mm^2.
CMOS-based sensor array chips provide new and attractive features as compared to todays standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.
Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of off-the-shelf TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable G
We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgra
A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analy
Power distribution systems are experiencing a large-scale integration of Converter-Interfaced Distributed Energy Resources (CIDERs). This complicates the analysis and mitigation of harmonics, whose creation and propagation are facilitated by the inte