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For a system-level design of Networks-on-Chip for 3D heterogeneous System-on-Chip (SoC), the locations of components, routers and vertical links are determined from an application model and technology parameters. In conventional methods, the two inputs are accounted for separately; here, we define an integrated problem that considers both application model and technology parameters. We show that this problem does not allow for exact solution in reasonable time, as common for many design problems. Therefore, we contribute a heuristic by proposing design steps, which are based on separation of intralayer and interlayer communication. The advantage is that this new problem can be solved with well-known methods. We use 3D Vision SoC case studies to quantify the advantages and the practical usability of the proposed optimization approach. We achieve up to 18.8% reduced white space and up to 12.4% better network performance in comparison to conventional approaches.
Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this paper, we propose to synthesize brain-network-inspired interconnections for la
The Network-on-Chips is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this work, we consider the generalized fault-tolerance topology generation problem, where the link or swi
Linear models are regularly used for mapping cores to tiles in a chip. System-on-Chip (SoC) design requires integration of functional units with varying sizes, but conventional models only account for identical-sized cores. Linear models cannot calcu
3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moores law scaling. 3D stacking promises potential gains in performance, power and cost but th
In the last years, it was demonstrated that neutral molecules can be loaded on a microchip directly from a supersonic beam. The molecules are confined in microscopic traps that can be moved smoothly over the surface of the chip. Once the molecules ar