اشترك بالحزمة الذهبية واحصل على وصول غير محدود شمرا أكاديميا
تسجيل مستخدم جديدCosmic test of sTGC detector prototype made in China for ATLAS experiment upgrade
87
0
0.0
(
0
)
اسأل ChatGPT حول البحث
ﻻ يوجد ملخص باللغة العربية
Following the Higgs particle discovery, the Large Hadron Collider complex will be upgraded in several phases allowing the luminosity to increase to $7 times 10^{34}cm^{-2}s^{-1}$. In order to adapt the ATLAS detector to the higher luminosity environment after the upgrade, part of the ATLAS muon end-cap system, the Small Wheel, will be replaced by the New Small Wheel. The New Small Wheel includes two kinds of detectors: small-strip Thin Gap Chambers and Micromegas. Shandong University, part of the ATLAS collaboration, participates in the construction of the ATLAS New Small Wheel by developing, producing and testing the performance of part of the small-strip Thin Gap Chambers. This paper describes the construction and cosmic-ray testing of small-strip Thin Gap Chambers in Shandong University.
قيم البحث
اقرأ أيضاً
This paper presents a readout system designed for testing the prototype of Small-Strip Thin Gap Chamber (sTGC), which is one of the main detector technologies used for ATLAS New-Small-Wheel Upgrade. This readout system aims at testing one full-size sTGC quadruplet with cosmic muon triggers.
A completely New Small Wheel (NSW) will be constructed for ATLAS Phase-1 upgrade. Small-Strip Thin-Gap-Chamber (sTGC) will devote to the trigger function of NSW. A full-size sTGC quadruplet consists of 4 layers, and will need 4 pad Front-End-Boards a
nd 4 strip Front-End-Boards for sTGC signals readout. The 8 boards should be readout simultaneously at a time. This paper presents the study of multi-layer sTGC test system, a FEB Driver Card (FEBDC) is designed for pFEB and sFEB boards handling. The design and test of FEBDC are described in details.
A new small-diameter Monitored Drift Tube (sMDT) chamber has been developed for the muon spectrometer of the ATLAS experiment to handle the higher collision rates expected at the CERN High Luminosity Large Hadron Collider (HL-LHC). This paper present
s measurements of the tracking resolution and hit efficiency of two prototype sMDT chambers constructed at the University of Michigan. Using cosmic-ray muons the sMDT tracking resolution of 103.7$pm8.1$ textmu m was measured for one chamber and 101.8$pm$7.8 textmu m for the other, compared with a design resolution of 106 textmu m. A further tracking resolution improvement to 83.4$pm$7.8 textmu m was obtained by using new high-gain readout electronics which will be added for HL-LHC. An average tracking efficiency of (98.5$pm$0.2)% was found for both chambers. The methodology used to determine the detector tracking resolution and efficiency, including reconstruction of sMDT data and a Geant4 simulation of the test chamber, is presented in detail.
To cope with the harsh environment foreseen at the high luminosity conditions of HL- LHC, the ATLAS pixel detector has to be upgraded to be fully efficient with a good granularity, a maximized geometrical acceptance and an high read out rate. LPNHE,
FBK and INFN are involved in the development of thin and edgeless planar pixel sensors in which the insensitive area at the border of the sensor is minimized thanks to the active edge technology. In this paper we report on two productions, a first one consisting of 200 {mu}m thick n-on-p sensors with active edge, a second one composed of 100 and 130 {mu}m thick n-on-p sensors. Those sensors have been tested on beam, both at CERN-SPS and at DESY and their performance before and after irradiation will be presented.
The Pad Front End Board (pFEB) and the Strip Front End Board (sFEB) are developed for the ATLAS Phase-I sTGC Trigger Upgrade. The pFEB is used to to gather and analyze pads trigger, and the sFEB is developed to accept the pad trigger to define the re
gions-of-interest for strips readout. The performance of p/sFEBs must be confirmed before they are mounted on the sTGC detector. We will present the scanning test system prototype which is designed according to the test requirements of the p/sFEB. In this test system prototype, a simulation signal board is developed to generate different types of signal to the p/sFEB. PC software and FPGA XADC cooperate to achieve the scan test of analog parameter.
سجل دخول لتتمكن من نشر تعليقات
التعليقات
جاري جلب التعليقات
سجل دخول لتتمكن من متابعة معايير البحث التي قمت باختيارها
