ترغب بنشر مسار تعليمي؟ اضغط هنا

Energy Efficient Tri-State CNFET Ternary Logic Gates

173   0   0.0 ( 0 )
 نشر من قبل Fazel Sharifi
 تاريخ النشر 2018
  مجال البحث الهندسة المعلوماتية
والبحث باللغة English




اسأل ChatGPT حول البحث

Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano devices are two feasible solutions to overcome these problems. In this paper, a novel method is presented to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, for example, adjusting the Carbon Nanontube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. In an effort to show a more detailed application of our approach, we design a 2-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, a power efficient ternary logic ALU has been design based on the proposed gates.

قيم البحث

اقرأ أيضاً

Memtranstor that correlates charge and magnetic flux via nonlinear magnetoelectric effects has a great potential in developing next-generation nonvolatile devices. In addition to multi-level nonvolatile memory, we demonstrate here that nonvolatile lo gic gates such as NOR and NAND can be implemented in a single memtranstor made of the Ni/PMN-PT/Ni heterostructure. After applying two sequent voltage pulses (X1, X2) as the logic inputs on the memtranstor, the output magnetoelectric voltage can be positive high (logic 1), positive low (logic 0), or negative (logic 0), depending on the levels of X1 and X2. The underlying physical mechanism is related to the complete or partial reversal of ferroelectric polarization controlled by inputting selective voltage pulses, which determines the magnitude and sign of the magnetoelectric voltage coefficient. The combined functions of both memory and logic could enable the memtranstor as a promising candidate for future computing systems beyond von Neumann architecture.
Magnetic analogue of electronic gates are advantageous in many ways. There is no electron leakage, higher switching speed and more energy saving in a magnetic logic device compared to a semiconductor one. Recently, we proposed a magnetic vortex trans istor and fan-out out devices based on carefully coupled magnetic vortices in isolated nanomagnetic disks. Here, we demonstrate a new type of magnetic logic gate based upon asymmetric vortex transistor by using micromagnetic simulation. Depending upon two main features (topology) of magnetic vortex, chirality and polarity, the network can behave like a tri-state buffer. Considering the asymmetric magnetic vortex Transistor as a unit, the logic gate has been formed where two such transistors are placed parallel and another one is placed at the output. Magnetic energy given in the input transistors is transferred to the output transistor with giant amplification, due to the movement of antivortex solitons through the magnetic stray field. The loss and gain of energy at the output transistor can be controlled only by manipulating the polarities of the middle vortices in input transistors. Due to the asymmetric energy transfer of the antivortex solitons, we have shown successful fan-in operation in this topologically symmetric system. A tri-state buffer gate with fan-in of two transistors can be formed. This gate can be used as a Switch to the logic circuit and it has technological importance for energy transfer to large scale vortex networks.
We present how basic logic gates including NAND, NOR and XOR gates can be implemented counterfactually. The two inputs (Bob and Charlie) and the output (Alice) of the proposed counterfactual logic gate are not within the same station but rather separ ated in three different locations. We show that there is no need to pre-arrange entanglement for the gate, and more importantly, there is no real physical particles traveling among Alice, Bob and Charlie during the information processing. Bob and Charlie only need to independently control the blocking and unblocking of the transmission channels that connect them to Alice. In this way, they can completely determine the state of a real photon at Alices end, thereby leading to implement a counterfactual logic gate. The functionality of a particular counterfactual logic gate is determined only by an appropriate design of Alices optical device. Furthermore, by utilizing the proposed counterfactual logic gates, we demonstrate how to counterfactually prepare the Greenberger-Horne-Zeilinger state and W state with three remote quantum objects, which are in superposition states of blocking and unblocking the transmission channel.
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic. It operates with zero static power dissipation and very low dynamic power dissipation owing to adiabatic switching. In previous numerical studies, we have eva luated the energy dissipation of basic AQFP logic gates and demonstrated sub-kBT switching energy, where kB is the Boltzmanns constant and T is the temperature, by integrating the product of the excitation current and voltage associated with the gates over time. However, this method is not applicable to complex logic gates, especially those in which the number of inputs is different from the number of outputs. In the present study, we establish a systematic method to evaluate the energy dissipation of general AQFP logic gates. In the proposed method, the energy dissipation is calculated by subtracting the energy dissipation of the peripheral circuits from that of the entire circuit. In this way, the energy change due to the interaction between gates, which makes it difficult to evaluate the energy dissipation, can be deducted. We evaluate the energy dissipation of a majority gate using this method.
Superparamagnetic tunnel junctions (SMTJs) have emerged as a competitive, realistic nanotechnology to support novel forms of stochastic computation in CMOS-compatible platforms. One of their applications is to generate random bitstreams suitable for use in stochastic computing implementations. We describe a method for digitally programmable bitstream generation based on pre-charge sense amplifiers. This generator is significantly more energy efficient than SMTJ-based bitstream generators that tune probabilities with spin currents and a factor of two more efficient than related CMOS-based implementations. The true randomness of this bitstream generator allows us to use them as the fundamental units of a novel neural network architecture. To take advantage of the potential savings, we codesign the algorithm with the circuit, rather than directly transcribing a classical neural network into hardware. The flexibility of the neural network mathematics allows us to adapt the network to the explicitly energy efficient choices we make at the device level. The result is a convolutional neural network design operating at $approx$ 150 nJ per inference with 97 % performance on MNIST -- a factor of 1.4 to 7.7 improvement in energy efficiency over comparable proposals in the recent literature.
التعليقات
جاري جلب التعليقات جاري جلب التعليقات
سجل دخول لتتمكن من متابعة معايير البحث التي قمت باختيارها
mircosoft-partner

هل ترغب بارسال اشعارات عن اخر التحديثات في شمرا-اكاديميا