The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphe
ne nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing.
The maximum oscillation frequency (fmax) quantifies the practical upper bound for useful circuit operation. We report here an fmax of 70 GHz in transistors using epitaxial graphene grown on the C-face of SiC. This is a significant improvement over Si
-face epitaxial graphene used in the prior high frequency transistor studies, exemplifying the superior electronics potential of C-face epitaxial graphene. Careful transistor design using a high {kappa} dielectric T-gate and self-aligned contacts, further contributed to the record-breaking fmax.
Graphene is generally considered to be a strong candidate to succeed silicon as an electronic material. However, to date, it actually has not yet demonstrated capabilities that exceed standard semiconducting materials. Currently demonstrated viable g
raphene devices are essentially limited to micron size ultrahigh frequency analog field effect transistors and quantum Hall effect devices for metrology. Nanoscopically patterned graphene tends to have disordered edges that severely reduce mobilities thereby obviating its advantage over other materials. Here we show that graphene grown on structured silicon carbide surfaces overcomes the edge roughness and promises to provide an inroad into nanoscale patterning of graphene. We show that high quality ribbons and rings can be made using this technique. We also report on progress towards high mobility graphene monolayers on silicon carbide for device applications.
