A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers
on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/{mu}m2 and approaches the depairing current density of Nb films.
New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stoplayers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (Ic) targeting
and reproducibility, eliminate aging, and eliminate pattern-dependent effects in Ic and tunneling characteristics of Nb/Al/AlOx/Nb junctions in integrated circuits. The latter effects were recently found in Nb-based JJs integrated into multilayered digital circuits. E.g., it was found that Josephson critical current density (Jc) may depend on the JJs environment, on the type and size of metal layers making contact to niobium base (BE) and counter electrodes (CE) of the junction, and also change with time. Such Jc variations within a circuit reduce circuit performance and yield, and restrict integration scale. This variability of JJs is explained as caused by hydrogen contamination of Nb layers during wafer processing, which changes the height and structural properties of AlOx tunnel barrier. Redistribution of hydrogen impurities between JJ electrodes and other circuit layers by diffusion along Nb wires and through contacts between layers causes long-term drift of Jc. At least two DSLs are required to completely protect JJs from impurity diffusion effects - right below the junction BE and right above the junction CE. The simplest and the most technologically convenient DSLs we have found are thin (from 3 nm to 10 nm) layers of Al. They were deposited in-situ under the BE layer, thus forming an Al/Nb/Al/AlOx/Nb penta-layer, and under the first wiring layer to junctions CE, thus forming an Al/Nb wiring bi-layer. A significant improvement of Jc uniformity on 150-mm wafer has also been obtained along with large improvements in Jc targeting and run-to-run reproducibility.
