We developed a multi-level lithography process to fabricate graphene p-n-p junctions with the novel geometry of contactless, suspended top gates. This fabrication procedure minimizes damage or doping to the single atomic layer, which is only exposed
to conventional resists and developers. The process does not require special equipment for depositing gate dielectrics or releasing sacrificial layers, and is compatible with annealing procedures that improve device mobility. Using this technique, we fabricate graphene devices with suspended local top gates, where the creation of high quality graphene p-n-p junctions is confirmed by transport data at zero and high magnetic fields.
