A Biological-Realtime Neuromorphic System in 28 nm CMOS using Low-Leakage Switched Capacitor Circuits

A switched-capacitor (SC) neuromorphic system for closed-loop neural coupling in 28 nm CMOS is presented, occupying 600 um by 600 um. It offers 128 input channels (i.e. presynaptic terminals), 8192 synapses and 64 output channels (i.e. neurons). Biologically realistic neuron and synapse dynam- ics are achieved via a faithful translation of the behavioural equations to SC circuits. As leakage currents significantly affect circuit behaviour at this technology node, dedicated compensation techniques are employed to achieve biological-realtime operation, with faithful reproduction of time constants of several 100 ms at room temperature. Power draw of the overall system is 1.9 mW.

Untersuchungen zur Implementierung von Bildverarbeitungsalgorithmen mittels pulsgekoppelter neuronaler Netze

This thesis deals with the study of image processing algorithms which can be implemented by pulse-coupled neural nets. The inspiration for this choice is taken from biological image processing, which achieves with little computational effort in highly parallel processes image analysis tasks such as object recognition, image segmentation, velocity and distance estimation, etc. Conventional, serially implemented algorithms either cannot realize those tasks at all or will expend significantly more effort. Because the first stages of the visual system comprise a sensor interface, they are comparatively accessible with respect to defining their transfer or processing function. Some of those processing functions or principles are to be used in hardware implementations, with the focus on duplicating especially the highly parallel processing.

OTA based 200 G{Omega} resistance on 700 {mu}m2 in 180 nm CMOS for neuromorphic applications

Generating an exponential decay function with a time constant on the order of hundreds of milliseconds is a mainstay for neuromorphic circuits. Usually, either subthreshold circuits or RC-decays based on transconductance amplifiers are used. In the latter case, transconductances in the 10 pS range are needed. However, state-of-the-art low-transconductance amplifiers still require too much circuit area to be applicable in neuromorphic circuits where >100 of these time constant circuits may be required on a single chip. We present a silicon verified operational transconductance amplifier that achieves a gm of 5 pS in only 700 {mu}m2, a factor of 10-100 less area than current examples. This allows a high-density integration of time constant circuits in target appliations such as synaptic learning or as driving circuit for neuromorphic memristor arrays.