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A steep-slope MoS2-nanoribbon MOSFET based on an intrinsic cold-contact effect

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 Added by Demetrio Logoteta
 Publication date 2020
  fields Physics
and research's language is English




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We propose a steep-slope MoS2-nanoribbon field-effect transistor that exploits a narrow-energy conduction band to intrinsically filter out the thermionic tail of the electron energy distribution. We study the device operation principle and the performance dependence on the design parameters through atomistic self-consistent quantum simulations. Our results indicate that the device can provide high ION/IOFF ratios, compatible with electronic applications, albeit biased at ultralow voltages of around 0.1 V.

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The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS2) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 {mu}A/{mu}m, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied.
We study field effect transistor characteristics in etched single layer MoS2 nanoribbon devices of width 50nm with ohmic contacts. We employ a SF6 dry plasma process to etch MoS2 nanoribbons using low etching (RF) power allowing very good control over etching rate. Transconductance measurements reveal a steep sub-threshold slope of 3.5V/dec using a global backgate. Moreover, we measure a high current density of 38 uA/um resulting in high on/off ratio of the order of 10^5. We observe mobility reaching as high as 50 cm^2/V.s with increasing source-drain bias.
Room-temperature Fermi-Dirac electron thermal excitation in conventional three-dimensional (3D) or two-dimensional (2D) semiconductors generates hot electrons with a relatively long thermal tail in energy distribution. These hot electrons set a fundamental obstacle known as the Boltzmann tyranny that limits the subthreshold swing (SS) and therefore the minimum power consumption of 3D and 2D field-effect transistors (FETs). Here, we investigated a novel graphene (Gr)-enabled cold electron injection where the Gr acts as the Dirac source to provide the cold electrons with a localized electron density distribution and a short thermal tail at room temperature. These cold electrons correspond to an electronic cooling effect with the effective electron temperature of ~145 K in the monolayer MoS2, which enable the transport factor lowering and thus the steep-slope switching (across for 3 decades with a minimum SS of 29 mV/decade at room temperature) for a monolayer MoS2 FET. Especially, a record-high sub-60-mV/decade current density (over 1 {mu}A/{mu}m) can be achieved compared to conventional steep-slope technologies such as tunneling FETs or negative capacitance FETs using 2D or 3D channel materials. Our work demonstrates the great potential of 2D Dirac-source cold electron transistor as an innovative steep-slope transistor concept, and provides new opportunities for 2D materials toward future energy-efficient nanoelectronics.
We report on the fabrication and characterization of synthesized multiwall MoS2 nanotube (NT) and nanoribbon (NR) field-effect transistors (FETs). The MoS2 NTs and NRs were grown by chemical transport, using iodine as a transport agent. Raman spectroscopy confirms the material as unambiguously MoS2 in NT, NR, and flake forms. Transmission electron microscopy was used to observe cross sections of the devices after electrical measurements and these were used in the interpretation of the electrical measurements allowing estimation of the current density. The NT and NR FETs demonstrate n-type behavior, with ON/OFF current ratios exceeding 10^3, and with current densities of 1.02 {mu}A/{mu}m, and 0.79 {mu}A/{mu}m at VDS = 0.3 V and VBG = 1 V, respectively. Photocurrent measurements conducted on a MoS2 NT FET, revealed short-circuit photocurrent of tens of nanoamps under an excitation optical power of 78 {mu}W and 488 nm wavelength, which corresponds to a responsivity of 460 {mu}A/W. A long channel transistor model was used to model the common-source characteristics of MoS2 NT and NR FETs and was shown to be consistent with the measured data.
Understanding the interfacial electrical properties between metallic electrodes and low dimensional semiconductors is essential for both fundamental science and practical applications. Here we report the observation of thickness reduction induced crossover of electrical contact at Au/MoS2 interfaces. For MoS2 thicker than 5 layers, the contact resistivity slightly decreases with reducing MoS2 thickness. By contrast, the contact resistivity sharply increases with reducing MoS2 thickness below 5 layers, mainly governed by the quantum confinement effect. It is found that the interfacial potential barrier can be finely tailored from 0.3 to 0.6 eV by merely varying MoS2 thickness. A full evolution diagram of energy level alignment is also drawn to elucidate the thickness scaling effect. The finding of tailoring interfacial properties with channel thickness represents a useful approach controlling the metal/semiconductor interfaces which may result in conceptually innovative functionalities.
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