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Register a new userSteep-slope Hysteresis-free Negative Capacitance MoS2 Transistors
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The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS2) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 {mu}A/{mu}m, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied.
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Room-temperature Fermi-Dirac electron thermal excitation in conventional three-dimensional (3D) or two-dimensional (2D) semiconductors generates hot electrons with a relatively long thermal tail in energy distribution. These hot electrons set a fundamental obstacle known as the Boltzmann tyranny that limits the subthreshold swing (SS) and therefore the minimum power consumption of 3D and 2D field-effect transistors (FETs). Here, we investigated a novel graphene (Gr)-enabled cold electron injection where the Gr acts as the Dirac source to provide the cold electrons with a localized electron density distribution and a short thermal tail at room temperature. These cold electrons correspond to an electronic cooling effect with the effective electron temperature of ~145 K in the monolayer MoS2, which enable the transport factor lowering and thus the steep-slope switching (across for 3 decades with a minimum SS of 29 mV/decade at room temperature) for a monolayer MoS2 FET. Especially, a record-high sub-60-mV/decade current density (over 1 {mu}A/{mu}m) can be achieved compared to conventional steep-slope technologies such as tunneling FETs or negative capacitance FETs using 2D or 3D channel materials. Our work demonstrates the great potential of 2D Dirac-source cold electron transistor as an innovative steep-slope transistor concept, and provides new opportunities for 2D materials toward future energy-efficient nanoelectronics.
We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, besides H2O and O2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.
The pressing quest for overcoming Boltzmann tyranny in low-power nanoscale electronics revived the thoughts of engineers of early 1930-s on the possibility of negative circuit constants. The concept of the ferroelectric-based negative capacitance (NC) devices triggered explosive activity in the field. However, most of the research addressed transient NC, leaving the basic question of the existence of the steady-state NC unresolved. Here we demonstrate that the ferroelectric nanodot capacitor hosts a stable two-domain state realizing the static reversible NC device thus opening routes for the extensive use of the NC in domain wall-based nanoelectronics.
Large capacitance enhancement is useful for increasing the gate capacitance of field-effect transistors (FETs) to produce low-energy-consuming devices with improved gate controllability. We report strong capacitance enhancement effects in a newly emerged two-dimensional channel material, molybdenum disulfide (MoS2). The enhancement effects are due to strong electron-electron interaction at the low carrier density regime in MoS2. We achieve about 50% capacitance enhancement in monolayer devices and 10% capacitance enhancement in bilayer devices. However, the enhancement effect is not obvious in multilayer (layer number >3) devices. Using the Hartree-Fock approximation, we illustrate the same trend in our inverse compressibility data.
Negative capacitance (NC) in ferroelectrics, which stems from the imperfect screening of polarization, is considered a viable approach to lower voltage operation in the field-effect transistors (FETs) used in logic switches. In this paper, we discuss the implications of the transient nature of negative capacitance for its practical application. It is suggested that the NC effect needs to be characterized at the proper time scale to identify the type of circuits where functional NC-FETs can be used effectively.
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