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Register a new userSilicon quantum computation based on magnetic dipolar coupling
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A dipolar gate alternative to the exchange gate based Kane quantum computer is proposed where the qubits are electron spins of shallow group V donors in silicon. Residual exchange coupling is treated as gate error amenable to quantum error correction, removing the stringent requirements on donor positioning characteristic of all silicon exchange-based implementations [B. Koiller et al., Phys. Rev. Lett. 88, 027903 (2002)]. Contrary to common speculation, such a scheme is scalable with no overhead in gating time even though it is based on long-range dipolar inter-qubit coupling.
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Addressability of spin qubits in a silicon double quantum dot setup in the (1,1) charge configuration relies on having a large difference between the Zeeman splittings of the electrons. When the difference is not sufficiently large, the rotating wave approximation becomes inaccurate. We consider a device working in this regime, with always-on exchange coupling, and describe how a CZ gate and arbitrary one-qubit gates which are robust against charge noise can be implemented by smoothly pulsing the microwave source, while eliminating the crosstalk. We find that the most significant deviations from the rotating wave approximation, which are analogous to the Bloch-Siegert shift in a two-level system, can be compensated using local virtual gates.
RF reflectometry offers a fast and sensitive method for charge sensing and spin readout in gated quantum dots. We focus in this work on the implementation of RF readout in accumulation-mode gate-defined quantum dots, where the large parasitic capacitance poses a challenge. We describe and test two methods for mitigating the effect of the parasitic capacitance, one by on-chip modifications and a second by off-chip changes. We demonstrate that these methods enable high-performance charge readout in Si/SiGe quantum dots, achieving a fidelity of 99.9% for a measurement time of 1 $mu$s.
Recent advances in quantum error correction (QEC) codes for fault-tolerant quantum computing cite{Terhal2015} and physical realizations of high-fidelity qubits in a broad range of platforms cite{Kok2007, Brown2011, Barends2014, Waldherr2014, Dolde2014, Muhonen2014, Veldhorst2014} give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based entirely on complementary metal-oxide-semiconductor (CMOS) technology, which is the basis for all modern processor chips. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin states of a single electron confined in a quantum dot, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout cite{Colless2013}. This system, based entirely on available technology and existing components, is compatible with general surface code quantum error correction cite{Terhal2015}, enabling large-scale universal quantum computation.
We demonstrate how gradient ascent pulse engineering optimal control methods can be implemented on donor electron spin qubits in Si semiconductors with an architecture complementary to the original Kanes proposal. We focus on the high-fidelity controlled-NOT (CNOT) gate and explicitly find its digitized control sequences by optimizing its fidelity over the external controls of the hyperfine A and exchange J interactions. This high-fidelity CNOT gate has an error of about $10^{-6}$, below the error threshold required for fault-tolerant quantum computation, and its operation time of 100ns is about 3 times faster than 297ns of the proposed global control scheme. It also relaxes significantly the stringent distance constraint of two neighboring donor atoms of 10~20nm as reported in the original Kanes proposal to about 30nm in which surface A and J gates may be built with current fabrication technology. The effects of the control voltage fluctuations, the dipole-dipole interaction and the electron spin decoherence on the CNOT gate fidelity are also discussed.
Spins in silicon quantum devices are promising candidates for large-scale quantum computing. Gate-based sensing of spin qubits offers compact and scalable readout with high fidelity, however further improvements in sensitivity are required to meet the fidelity thresholds and measurement timescales needed for the implementation of fast-feedback in error correction protocols. Here, we combine radio-frequency gate-based sensing at 622 MHz with a Josephson parametric amplifier (JPA), that operates in the 500-800 MHz band, to reduce the integration time required to read the state of a silicon double quantum dot formed in a nanowire transistor. Based on our achieved signal-to-noise ratio (SNR), we estimate that singlet-triplet single-shot readout with an average fidelity of 99.7% could be performed in 1 $mu$s, well-below the requirements for fault-tolerant readout and 30 times faster than without the JPA. Additionally, the JPA allows operation at a lower RF power while maintaining identical SNR. We determine a noise temperature of 200 mK with a contribution from the JPA (25%), cryogenic amplifier (25%) and the resonator (50%), showing routes to further increase the read-out speed.
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