No Arabic abstract
The potential of Si and SiGe-based devices for the scaling of quantum circuits is tainted by device variability. Each device needs to be tuned to operation conditions. We give a key step towards tackling this variability with an algorithm that, without modification, is capable of tuning a 4-gate Si FinFET, a 5-gate GeSi nanowire and a 7-gate SiGe heterostructure double quantum dot device from scratch. We achieve tuning times of 30, 10, and 92 minutes, respectively. The algorithm also provides insight into the parameter space landscape for each of these devices. These results show that overarching solutions for the tuning of quantum devices are enabled by machine learning.
Porting code from CPU to GPU is costly and time-consuming; Unless much time is invested in development and optimization, it is not obvious, a priori, how much speed-up is achievable or how much room is left for improvement. Knowing the potential speed-up a priori can be very useful: It can save hundreds of engineering hours, help programmers with prioritization and algorithm selection. We aim to address this problem using machine learning in a supervised setting, using solely the single-threaded source code of the program, without having to run or profile the code. We propose a static analysis-based cross-architecture performance prediction framework (Static XAPP) which relies solely on program properties collected using static analysis of the CPU source code and predicts whether the potential speed-up is above or below a given threshold. We offer preliminary results that show we can achieve 94% accuracy in binary classification, in average, across different thresholds
Deep reinforcement learning is an emerging machine learning approach which can teach a computer to learn from their actions and rewards similar to the way humans learn from experience. It offers many advantages in automating decision processes to navigate large parameter spaces. This paper proposes a novel approach to the efficient measurement of quantum devices based on deep reinforcement learning. We focus on double quantum dot devices, demonstrating the fully automatic identification of specific transport features called bias triangles. Measurements targeting these features are difficult to automate, since bias triangles are found in otherwise featureless regions of the parameter space. Our algorithm identifies bias triangles in a mean time of less than 30 minutes, and sometimes as little as 1 minute. This approach, based on dueling deep Q-networks, can be adapted to a broad range of devices and target transport features. This is a crucial demonstration of the utility of deep reinforcement learning for decision making in the measurement and operation of quantum devices.
Recent advances in quantum error correction (QEC) codes for fault-tolerant quantum computing cite{Terhal2015} and physical realizations of high-fidelity qubits in a broad range of platforms cite{Kok2007, Brown2011, Barends2014, Waldherr2014, Dolde2014, Muhonen2014, Veldhorst2014} give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based entirely on complementary metal-oxide-semiconductor (CMOS) technology, which is the basis for all modern processor chips. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin states of a single electron confined in a quantum dot, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout cite{Colless2013}. This system, based entirely on available technology and existing components, is compatible with general surface code quantum error correction cite{Terhal2015}, enabling large-scale universal quantum computation.
The boundary of topological superconductors might lead to the appearance of Majorana edge modes, whose non-trivial exchange statistics can be used for topological quantum computing. In branched nanowire networks one can exchange Majorana states by time-dependently tuning topologically non-trivial parameter regions. In this work, we simulate the exchange of four Majorana modes in T-shaped junctions made out of p-wave superconducting Rashba wires. We derive concrete experimental predictions for (quasi-)adiabatic braiding times and determine geometric conditions for successful Majorana exchange processes. Contrary to the widespread opinion, we show for the first time that in the adiabatic limit the gating time needs to be smaller than the inverse of the squared superconducting order parameter and scales linearly with the gating potential. Further, we show how to circumvent the formation of additional Majorana modes in branched nanowire systems, arising at wire intersection points of narrow junctions. Finally, we propose a multi qubit setup, which allows for universal and in particular topologically protected quantum computing.
The epitaxial growth of germanium on silicon leads to the self-assembly of SiGe nanocrystals via a process that allows the size, composition and position of the nanocrystals to be controlled. This level of control, combined with an inherent compatibility with silicon technology, could prove useful in nanoelectronic applications. Here we report the confinement of holes in quantum-dot devices made by directly contacting individual SiGe nanocrystals with aluminium electrodes, and the production of hybrid superconductorsemiconductor devices, such as resonant supercurrent transistors, when the dot is strongly coupled to the electrodes. Charge transport measurements on weakly coupled quantum dots reveal discrete energy spectra, with the confined hole states displaying anisotropic gyromagnetic factors and strong spin-orbit coupling strength with pronounced gate-voltage and magnetic-field dependence.