No Arabic abstract
Conventional CMOS technology operated at cryogenic conditions has recently attracted interest for its uses in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK, extracting I/V characteristics, threshold voltages, and transconductance values, as well as observing their temperature dependence. We find that CMOS devices remain fully operational down to these temperatures, although we observe hysteresis effects in some devices. The measurements described in this paper can be used to inform the future design of CMOS devices intended to be operated in this deep cryogenic regime.
This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300, 77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems.
We report on the experimental study made on a successive prototype of High-Voltage CMOS (HV-CMOS) ATLASPix2 sensor for the tracking detector application, developed with 180 nm feature size. These sensors are to qualify mainly the peripheral data processing blocks (e.g. Command Decoder, Trigger Buffer, etc.). It is a smaller version of 24 X 36 pixelated sensor in comparison to the earlier generation of ATLASPix1 fabricated in both ams AG, Austria, and TSI Semiconductors, USA. While ams produced ATLASPix2 showed breakdown voltage 50 V in nonirradiated condition as it was seen on its predecessors ATLASpix1, TSI produced prototypes reported breakdown voltage greater than 100 V. The chosen wafer of MCz 20 Ohm.cm P-type substrate resistivity can deplete a few tenths of um, where the process-driven surface damage can have a greater impact on device operating conditions before and after irradiation. In an aim to understand device intrinsic performance at the irradiated case, a dedicated neutron irradiation campaign has been made at JSI for different fluences. Characterizations have been performed at different temperatures after irradiation to analyze the leakage current and breakdown voltage before and after irradiation. TSI prototypes showed a breakdown voltage decrease 90 V due to impact ionization and enhanced effective doping concentration. Results demonstrated for the neutron-irradiated devices up to the fluence of 2 X 10^15 neq/cm2 can still safely be operated at a voltage high enough to allow for high efficiency. Accelerated Annealing steps also made on selective irradiated ATLASPix2 samples, equivalent to more than two years of room-temperature annealing (at 20 degC), and they showed the reassuring expected breakdown voltage increase and damage constant rate alpha^* (geometry dependent) decrease, driven by the beneficial annealing.
This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2,K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4,K and 4.2,K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77,K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.
This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150,nm CMOS process. DMAPS exploit high voltage and/or high resistivity inclusion of modern CMOS technologies to achieve substantial depletion in the sensing volume. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade in 2025 for the High Luminosity Large Hadron Collider (HL-LHC). This type of devices has a lower production cost and lower material budget compared to presently used hybrid designs. In this work, the chip architecture will be described followed by the characterization of the different pre-amplifier and discriminator flavors with an external injection signal and an iron source (5.9,keV x-rays).
Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.