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Register a new userReal-Time Phase Correction based on FPGA in the Beam Position and Phase Measurement System
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A fully digital beam position and phase measurement (BPPM) system was designed for the linear accelerator (LINAC) in Accelerator Driven Sub-critical System (ADS) in China. Phase information is obtained from the summed signals from four pick-ups of the Beam Position Monitor (BPM). Considering that the delay variations of different analog circuit channels would introduce phase measurement errors, we propose a new method to tune the digital waveforms of four channels before summation and achieve real-time error correction. The process is based on the vector rotation method and implemented within one single Field Programmable Gate Array (FPGA) device. Tests were conducted to evaluate this correction method and the results indicate that a phase correction precision better than +/- 0.3 degree over the dynamic range from -60 dBm to 0 dBm is achieved.
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Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging, which requires high position and energy precision, as well as good flexibility and efficiency of the electronics. This paper presents the design of a digital signal processing logic for a marmoset brain PET system based on LYSO crystal arrays, SiPMs, and the resistive network readout method. We implement 32-channel signal processing in a single Xilinx Artix-7 Field-Programmable Gate Array (FPGA). The logic is designed to support four online modes which are regular data processing mode, flood map construction mode, energy spectrum construction mode, and raw data mode. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal locating, events filtering, and synchronization detection. Furthermore, a series of online corrections is also integrated, such as photon peak correction to 511 keV and time measurement result correction with crystal granularity. A Gigabit Ethernet interface is utilized for data transfer, Look-Up Tables (LUTs) configuration, and command issuing. The pipeline logic works at 125 MHz with a signal processing capability beyond the required data rate of 1,000,000 events/s/channel. A series of initial tests are conducted. The results indicate that the logic design meets the application requirement.
An FPGA-based online trigger system has been developed for the COMET Phase-I experiment. This experiment searches for muon-to-electron conversion, which has never been observed yet. A drift chamber and trigger counters detect a mono-energetic electron from the conversion process in a 1-T solenoidal magnetic field. A highly intense muon source is applied to reach unprecedented experimental sensitivity. It also generates undesirable background particles, and a trigger rate due to these particles is expected to be much higher than an acceptable trigger rate in the data acquisition system. By using hit information from the drift chamber too, the online trigger system efficiently suppresses a background trigger rate while keeping signal-event acceptance large. A characteristic of this system is the utilization of the machine learning technique in the form of look-up tables on hardware. An initial simulation study indicates that the signal-event acceptance of the online trigger is 96% while the background trigger rate is reduced from over $90,mathrm{kHz}$ to $13,mathrm{kHz}$. For this scenario, we have produced trigger-related electronics that construct a distributed trigger architecture. The total latency of the trigger system was estimated to be $3.2,mathrm{mu s}$, and the first operation test was carried out by using a part of the drift-chamber readout region.
A prototype of DIRC-like Time-of-Flight detector (DTOF), including a pico-second time measurement electronics, is developed and tested preliminarily. The basic structure of DTOF is composed of a fused silica radiator connected to fast micro-channel plate PMTs (MCP-PMT), and readout by a dedicated FPGA (Field Programmable Gate Array) based front-end electronics. The full electronics chain consists of a programmable differential amplifier, a dual-threshold differential discriminator, and a timestamp Time-to-Digital convertor. By splitting a MCP-PMT output signal into two identical electronics chains, the coincidence time resolution (CTR) of pure electronics was measured as 5.6 ps. By the beam test in H4 (150GeV/c, Muon) at CERN, the intrinsic CTR of the whole detector prototype reaches 15.0 ps without using time-amplitude correction. The test results demonstrate that the FPGA based front-end electronics could achieve an excellent time performance for TOF detectors. It is very compact, cost effective with a high multi-channel capacity and short measurement dead time, which is very suitable for practical applications of large-scale high performance TOF detectors in particle physics spectrometer.
In this article it is presented an FPGA based $M$ulti-$V$oltage $T$hreshold (MVT) system which allows of sampling fast signals ($1-2$ ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time measurement of $20$ ps RMS and reconstruct charge of signals, using a simple approach, with deviation from real value smaller than 10$%$. Utilization of the differential inputs of an FPGA chip as comparators together with an implementation of a TDC inside an FPGA allowed us to achieve a compact multi-channel system characterized by low power consumption and low production costs. This paper describes realization and functioning of the system comprising 192-channel TDC board and a four mezzanine cards which split incoming signals and discriminate them. The boards have been used to validate a newly developed Time-of-Flight Positron Emission Tomography system based on plastic scintillators. The achieved full system time resolution of $sigma$(TOF) $approx 68$ ps is by factor of two better with respect to the current TOF-PET systems.
A novel approach to tomographic data processing has been developed and evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose a system in which there is no need for powerful, local to the scanner processing facility, capable to reconstruct images on the fly. Instead we introduce a Field Programmable Gate Array (FPGA) System-on-Chip (SoC) platform connected directly to data streams coming from the scanner, which can perform event building, filtering, coincidence search and Region-Of-Response (ROR) reconstruction by the programmable logic and visualization by the integrated processors. The platform significantly reduces data volume converting raw data to a list-mode representation, while generating visualization on the fly.
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