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Register a new userElectron-beam patterning of polymer electrolyte films to make multiple nanoscale gates for nanowire transistors
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We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO$_{4}$ polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap which reduces parasitic effects and enables multiple, independently controllable gates. The methods simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices.
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Control of atomic-scale interfaces between materials with distinct electronic structures is crucial for the design and fabrication of most electronic devices. In the case of two-dimensional (2D) materials, disparate electronic structures can be realized even within a single uniform sheet, merely by locally applying different vertical bias voltages. Indeed, it has been suggested that nanoscale electronic patterning in a single sheet can be achieved by placing the 2D material on a suitably pre-patterned substrate, exploiting the sensitivity of 2D materials to their environment via band alignment, screening or hybridization. Here, we utilize the inherently nano-structured single layer (SL) and bilayer (BL) graphene on silicon carbide to laterally tune the electrostatic gating of adjacent SL tungsten disulphide (WS$_2$) in a van der Waals heterostructure. The electronic band alignments are mapped in energy and momentum space using angle-resolved photoemission with a spatial resolution on the order of 500~nm (nanoARPES). We find that the SL WS$_2$ band offsets track the work function of the underlying SL and BL graphene, and we relate such changes to observed lateral patterns of exciton and trion luminescence from SL WS$_2$, demonstrating ultimate control of optoelectronic properties at the nanoscale.
We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favourable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.
Interfacial charge transfer plays an essential role in establishing the relative alignment of the metal Fermi level and the energy bands of organic semiconductors. While the details remain elusive in many systems, this charge transfer has been inferred in a number of photoemission experiments. We present electronic transport measurements in very short channel ($L < 100$ nm) transistors made from poly(3-hexylthiophene) (P3HT). As channel length is reduced, the evolution of the contact resistance and the zero-gate-voltage conductance are consistent with such charge transfer. Short channel conduction in devices with Pt contacts is greatly enhanced compared to analogous devices with Au contacts, consistent with charge transfer expectations. Alternating current scanning tunneling microscopy (ACSTM) provides further evidence that holes are transferred from Pt into P3HT, while much less charge transfer takes place at the Au/P3HT interface.
We report electrical characterization of monolayer molybdenum disulfide (MoS2) devices using a thin layer of polymer electrolyte consisting of poly(ethylene oxide) (PEO) and lithium perchlorate (LiClO4) as both a contact-barrier reducer and channel mobility booster. We find that bare MoS2 devices (without polymer electrolyte) fabricated on Si/SiO2 have low channel mobility and large contact resistance, both of which severely limit the field-effect mobility of the devices. A thin layer of PEO/ LiClO4 deposited on top of the devices not only substantially reduces the contact resistance but also boost the channel mobility, leading up to three-orders-of-magnitude enhancement of the field-effect mobility of the device. When the polymer electrolyte is used as a gate medium, the MoS2 field-effect transistors exhibit excellent device characteristics such as a near ideal subthreshold swing and an on/off ratio of 106 as a result of the strong gate-channel coupling.
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