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Register a new userLarge Area Roller Embossing of Multilayered Ceramic Green Composites
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EDA Publishing Association
Publication date
2008
fields
Informatics Engineering
and research's language is
English
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In this paper, we will report our achievements in developing large area patterning of multilayered ceramic green composites using roller embossing. The aim of our research is to pattern large area ceramic green composites using a modified roller laminating apparatus, which is compatible with screen printing machines, for integration of embossing and screen printing. The instrumentation of our roller embossing apparatus, as shown in Figure1, consists of roller 1 and rollers 2. Roller 1 is heated up to the desired embossing temperature ; roller 2 is, however, kept at room temperature. The mould is a nickel template manufactured by plating nickel-based micro patterns (height : 50 $mu$m) on a nickel film (thickness : 70 $mu$m) ; the substrate for the roller embossing is a multilayered Heraeus Heralock HL 2000 ceramic green composite. Comparing with the conventional simultaneous embossing, the advantages of roller embossing include : (1) low embossing force ; (2) easiness of demoulding ; (3) localized area in contact with heater ; and etc. We have demonstrated the capability of large area roller embossing with a panel size of 150mmx 150mm on the mentioned substrate. We have explored and confirmed the impact of parameters (feed speed, temperature of roller and applied pressure) to the pattern quality of roller embossing. Furthermore, under the optimized process parameters, we characterized the variations of pattern dimension over the panel area, and calculated a scaling factor in order to make the panel compatible with other processes. Figure 2 shows the embossed patterns on a 150mmx 150mm green ceramic panel.
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Multilayered ceramic substrates with embedded micro patterns are becoming increasingly important, for example, in harsh environment electronics and microfluidic devices. Fabrication of these embedded micro patterns, such as micro channels, cavities and vias, is a challenge. This study focuses on the process of patterning micro features on ceramic green substrates using micro embossing. A ceramic green tape that possessed near-zero shrinkage in the x-y plane was used, six layers of which were laminated as the embossing substrate. The process parameters that impact on the pattern fidelity were investigated and optimized in this study. Micro features with line-width as small as several micrometers were formed on the ceramic green substrates. The dynamic thermo-mechanical analysis indicated that extending the holding time at certain temperature range would harden the green substrates with little effect on improving the embossing fidelity. Ceramic substrates with embossed micro patterns were obtain d after co-firing. The embedded micro channels were also obtained by laminating the green tapes on the embossed substrates.
Today, hot embossing and injection molding belong to the established plastic molding processes in microengineering. Based on experimental findings, a variety of microstructures have been replicated so far using the processes. However, with increasing requirements regarding the embossing surface and the simultaneous decrease of the structure size down into the nanorange, increasing know-how is needed to adapt hot embossing to industrial standards. To reach this objective, a German-Canadian cooperation project has been launched to study hot embossing theoretically by a process simulation and experimentally. The present publication shall report about the first results of the simulation - the modeling and simulation of large area replication based on an eight inch microstructured mold.
Micro-indentation test with a micro flat-end cone indenter was employed to simulate micro embossing process and investigate the thermo-mechanical response of ceramic green substrates. The laminated low temperature co-fired ceramic green tapes were used as the testing material ; the correlations of indentation depth versus applied force and applied stress at the temperatures of 25 degrees C and 75degrees C were studied. The results showed that permanent indentation cavities could be formed at temperatures ranging from 25 degrees C to 75 degrees C, and the depth of cavities created was applied force, temperature and dwell time dependent. Creep occurred and made a larger contribution to the plastic deformation at elevated temperatures and high peak loads. There was instantaneous recovery during the unloading and retarded recovery in the first day after indentation. There was no significant pile-up due to material flow observed under compression at the temperature up to 75 degrees C. The plastic deformation was the main cause for formation of cavity on the ceramic green substrate under compression. The results can be used as a guideline for embossing ceramic green substrates.
In large area micro hot embossing, the process temperature plays a critical role to both the local fidelity of microstructure formation and global uniformity. The significance of low temperature hot embossing is to improve global flatness of embossed devices. This paper reports on experimental studies of polymer deformation and relaxation in micro embossing when the process temperatures are below or near its glass transition temperature (Tg). In this investigation, an indentation system and a micro embosser were used to investigate the relationship of microstructure formation versus process temperature and load pressure. The depth of indentation was controlled and the load force at a certain indentation depth was measured. Experiments were carried out using 1 mm thick PMMA films with the process temperature ranging from Tg-55 degrees C to Tg +20 degrees C. The embossed structures included a single micro cavity and groups of micro cavity arrays. It was found that at temperature of Tg-55 degrees C, elastic deformation dominated the formation of microstructures and significant relaxation happened after embossing. From Tg-20 degrees C to Tg, plastic deformation dominated polymer deformation, and permanent cavities could be formed on PMMA substrates without obvious relaxation. However, the formation of protrusive structures as micro pillars was not complete since there was little polymer flow. With an increase in process temperature, microstructure could be formed under lower loading pressure. Considering the fidelity of a single microstructure and global flatness of embossed substrates, micro hot embossing at a low process temperature, but with good fidelity, should be preferred.
Spin Transfer Torque MRAMs are attractive due to their non-volatility, high density and zero leakage. However, STT-MRAMs suffer from poor reliability due to shared read and write paths. Additionally, conflicting requirements for data retention and write-ability (both related to the energy barrier height of the magnet) makes design more challenging. Furthermore, the energy barrier height depends on the physical dimensions of the free layer. Any variations in the dimensions of the free layer lead to variations in the energy barrier height. In order to address poor reliability of STT-MRAMs, usage of Error Correcting Codes (ECC) have been proposed. Unlike traditional CMOS memory technologies, ECC is expected to correct both soft and hard errors in STT_MRAMs. To achieve acceptable yield with low write power, stronger ECC is required, resulting in increased number of encoded bits and degraded memory efficiency. In this paper, we propose Failure aware ECC (FaECC), which masks permanent faults while maintaining the same correction capability for soft errors without increased encoded bits. Furthermore, we investigate the impact of process variations on run-time reliability of STT-MRAMs. We provide an analysis on the impact of process variations on the life-time of the free layer and retention failures. In order to analyze the effectiveness of our methodology, we developed a cross-layer simulation framework that consists of device, circuit and array level analysis of STT-MRAM memory arrays. Our results show that using FaECC relaxes the requirements on the energy barrier height, which reduces the write energy and results in smaller access transistor size and memory array area. Keywords: STT-MRAM, reliability, Error Correcting Codes, ECC, magnetic memory
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