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Register a new userSurface-Electrode Architecture for Ion-Trap Quantum Information Processing
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We investigate a surface-mounted electrode geometry for miniature linear radio frequency Paul ion traps. The electrodes reside in a single plane on a substrate, and the pseudopotential minimum of the trap is located above the substrate at a distance on order of the electrodes lateral extent or separation. This architecture provides the possibility to apply standard microfabrication principles to the construction of multiplexed ion traps, which may be of particular importance in light of recent proposals for large-scale quantum computation based on individual trapped ions.
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We demonstrate confinement of individual atomic ions in a radio-frequency Paul trap with a novel geometry where the electrodes are located in a single plane and the ions confined above this plane. This device is realized with a relatively simple fabrication procedure and has important implications for quantum state manipulation and quantum information processing using large numbers of ions. We confine laser-cooled Mg-24 ions approximately 40 micrometer above planar gold electrodes. We measure the ions motional frequencies and compare them to simulations. From measurements of the escape time of ions from the trap, we also determine a heating rate of approximately five motional quanta per millisecond for a trap frequency of 5.3 MHz.
In this study, we report the first Cu-filled through silicon via (TSV) integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrodes numbers and evolving complexity. The integration of TSVs reduces the form factor of ion trap by more than 80%, minimizing parasitic capacitance from 32 to 3 pF. A low RF dissipation is achieved in spite of the absence of ground screening layer. The entire fabrication process is on 12-inch wafer and compatible with established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (~30 minutes) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.
Two-dimensional crystals of trapped ions are a promising system with which to implement quantum simulations of challenging problems such as spin frustration. Here, we present a design for a surface-electrode elliptical ion trap which produces a 2-D ion crystal and is amenable to microfabrication, which would enable higher simulated coupling rates, as well as interactions based on magnetic forces generated by on-chip currents. Working in an 11 K cryogenic environment, we experimentally verify to within 5% a numerical model of the structure of ion crystals in the trap. We also explore the possibility of implementing quantum simulation using magnetic forces, and calculate J-coupling rates on the order of 10^3 / s for an ion crystal height of 10 microns, using a current of 1 A.
Atomic ions trapped in ultra-high vacuum form an especially well-understood and useful physical system for quantum information processing. They provide excellent shielding of quantum information from environmental noise, while strong, well-controlled laser interactions readily provide quantum logic gates. A number of basic quantum information protocols have been demonstrated with trapped ions. Much current work aims at the construction of large-scale ion-trap quantum computers using complex microfabricated trap arrays. Several groups are also actively pursuing quantum interfacing of trapped ions with photons.
We describe a novel monolithic ion trap that combines the flexibility and scalability of silicon microfabrication technologies with the superior trapping characteristics of traditional four-rod Paul traps. The performace of the proposed microfabricated trap approaches that of the macroscopic structures. The fabrication process creates an angled through-chip slot which allows backside ion loading and through-laser access while avoiding surface light scattering and dielectric charging. The trap geometry and dimensions are optimized for confining long ion chains with equal ion spacing [G.-D. Lin, et al., Europhys. Lett. 86, 60004 (2009)]. Control potentials have been derived to produce linear, equally spaced ion chains of up to 50 ions spaced at 10 um. With the deep trapping depths achievable in this design, we expect that these chains will be sufficiently long-lived to be used in quantum simulations of magnetic systems [E.E. Edwards, et al., Phys. Rev. B 82, 060412(R) (2010)]. The trap is currently being fabricated at Georgia Tech using VLSI techniques.
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