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Register a new userSub-threshold channels at the edges of nanoscale triple-gate silicon transistors
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We investigate by low-temperature transport experiments the sub-threshold behavior of triple-gate silicon field-effect transistors. These three-dimensional nano-scale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers, down to 50x60x35 nm^3. Conductance versus gate voltage show Coulomb-blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analysis, we conclude that sub-threshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner-effect.
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The definition of the intrinsic cut-off frequency ($f_T$) based on the current gain equals to one (0 dB) is critically analyzed. A condition for the validity of the quasi-static estimation of $f_T$ is established in terms of the temporal variations of the electric charge and electric flux on the drain, source and gate terminals. Due to the displacement current, an electron traversing the channel length generates a current pulse of finite temporal width. For electron devices where the intrinsic delay time of the current after a transient perturbation is comparable to such width, the displacement currents cannot be neglected and the quasi-static approximation becomes inaccurate. We provide numerical results for some ballistic transistors where the estimation of $f_T$ under the quasi-static approximation can be one order of magnitude larger than predictions obtained from a time-dependent numerical simulations of the intrinsic delay time (including particle and displacement currents). In other ballistic transistors, we show that the gate current phasor can be smaller than the drain one at all frequencies, giving no finite value for $f_T$.
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