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Register a new userPerformance of a spin-based insulated gate field effect transistor
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Added by
Michael E. Flatt\\'e
Publication date
2006
fields
Physics
and research's language is
English
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Fundamental physical properties limiting the performance of spin field effect transistors are compared to those of ordinary (charge-based) field effect transistors. Instead of raising and lowering a barrier to current flow these spin transistors use static spin-selective barriers and gate control of spin relaxation. The different origins of transistor action lead to distinct size dependences of the power dissipation in these transistors and permit sufficiently small spin-based transistors to surpass the performance of charge-based transistors at room temperature or above. This includes lower threshold voltages, smaller gate capacitances, reduced gate switching energies and smaller source-drain leakage currents.
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A recent e-print (cond-mat/0604532) presented a proposed Comment to Applied Physics Letters on our publication Appl. Phys. Lett. 88, 162503 (2006), cond-mat/0603260. Here is our Response. As the proposed Comment has now been rejected by Applied Physics Letters, neither the Comment nor the Response will be published in Applied Physics Letters in this form.
The performance of field effect transistors based on an single graphene ribbon with a constriction and a single back gate are studied with the help of atomistic models. It is shown how this scheme, unlike that of traditional carbon-nanotube-based transistors, reduces the importance of the specifics of the chemical bonding to the metallic electrodes in favor of the carbon-based part of device. The ultimate performance limits are here studied for various constriction and metal-ribbon contact models. In particular we show that, even for poorly contacting metals, properly taylored constrictions can give promising values for both the on-conductance and the subthreshold swing.
The field-effect mobility of graphene devices is discussed. We argue that the graphene ballistic mean free path can only be extracted by taking into account both, the electrical characteristics and the channel length dependent mobility. In doing so we find a ballistic mean free path of 300nm at room-temperature for a carrier concentration of ~1e12/cm2 and that a substantial series resistance of around 300ohmum has to be taken into account. Furthermore, we demonstrate first quantum capacitance measurements on single-layer graphene devices.
We present an analytical device model for a graphene bilayer field-effect transistor (GBL-FET) with a graphene bilayer as a channel, and with back and top gates. The model accounts for the dependences of the electron and hole Fermi energies as well as energy gap in different sections of the channel on the bias back-gate and top-gate voltages. Using this model, we calculate the dc and ac source-drain currents and the transconductance of GBL-FETs with both ballistic and collision dominated electron transport as functions of structural parameters, the bias back-gate and top-gate voltages, and the signal frequency. It is shown that there are two threshold voltages, $V_{th,1}$ and $V_{th,2}$, so that the dc current versus the top-gate voltage relation markedly changes depending on whether the section of the channel beneath the top gate (gated section) is filled with electrons, depleted, or filled with holes. The electron scattering leads to a decrease in the dc and ac currents and transconductances, whereas it weakly affects the threshold frequency. As demonstrated, the transient recharging of the gated section by holes can pronouncedly influence the ac transconductance resulting in its nonmonotonic frequency dependence with a maximum at fairly high frequencies.
Integrating negative capacitance (NC) into the field-effect transistors promises to break fundamental limits of power dissipation known as Boltzmann tyranny. However, realization of the stable static negative capacitance in the non-transient regime without hysteresis remains a daunting task. Here we show that the failure to implement the NC stems from the lack of understanding that its origin is fundamentally related with the inevitable emergence of the domain state. We put forth an ingenious design for the ferroelectric domain-based field-effect transistor with the stable reversible static negative capacitance. Using dielectric coating of the ferroelectric capacitor enables the tunability of the negative capacitance improving tremendously the performance of the field-effect transistors.
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