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In Variational Quantum Simulations, the construction of a suitable parametric quantum circuit is subject to two counteracting effects. The number of parameters should be small for the device noise to be manageable, but also large enough for the circuit to be able to represent the solution. Dimensional expressivity analysis can optimize a candidate circuit considering both aspects. In this article, we will first discuss an inductive construction for such candidate circuits. Furthermore, it is sometimes necessary to choose a circuit with fewer parameters than necessary to represent all relevant states. To characterize such circuits, we estimate the best-approximation error using Voronoi diagrams. Moreover, we discuss a hybrid quantum-classical algorithm to estimate the worst-case best-approximation error, its complexity, and its scaling in state space dimensionality. This allows us to identify some obstacles for variational quantum simulations with local optimizers and underparametrized circuits, and we discuss possible remedies.
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Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this paper, we develop a method to analyze the dimensional expressivity of parametric quantum circuits. Our technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBMs quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.
A general method to mitigate the effect of errors in quantum circuits is outlined. The method is developed in sight of characteristics that an ideal method should possess and to ameliorate an existing method which only mitigates state preparation and measurement errors. The method is tested on different IBM Q quantum devices, using randomly generated circuits with up to four qubits. A large majority of results show significant error mitigation.
We reapply our approach to designing nanophotonic quantum memories to formulate an optical network that autonomously protects a single logical qubit against arbitrary single-qubit errors. Emulating the 9 qubit Bacon-Shor subsystem code, the network replaces the traditionally discrete syndrome measurement and correction steps by continuous, time-independent optical interactions and coherent feedback of unitarily processed optical fields.
Noise in existing quantum processors only enables an approximation to ideal quantum computation. However, these approximations can be vastly improved by error mitigation, for the computation of expectation values, as shown by small-scale experimental demonstrations. However, the practical scaling of these methods to larger system sizes remains unknown. Here, we demonstrate the utility of zero-noise extrapolation for relevant quantum circuits using up to 26 qubits, circuit depths of 60, and 1080 CNOT gates. We study the scaling of the method for canonical examples of product states and entangling Clifford circuits of increasing size, and extend it to the quench dynamics of 2-D Ising spin lattices with varying couplings. We show that the efficacy of the error mitigation is greatly enhanced by additional error suppression techniques and native gate decomposition that reduce the circuit time. By combining these methods, we demonstrate an accuracy in the approximate quantum simulation of the quench dynamics that surpasses the classical approximations obtained from a state-of-the-art 2-D tensor network method. These results reveal a path to a relevant quantum advantage with noisy, digital, quantum processors.
Quantum error correction (QEC) is fundamental for quantum information processing but entails a substantial overhead of classically-controlled quantum operations, which can be architecturally cumbersome to accommodate. Here we discuss a novel approach to designing elementary QEC memory cells, in which all control operations are performed autonomously by an embedded optical feedback loop. Our approach is natural for nanophotonic implementations in which each qubit can be coupled to its own optical resonator, and our design for a memory cell based on the quantum bit-flip or phase-flip code requires only five qubit-cavities (three for the register and two for the controller) connected by wave-guides. The photonic QEC circuit is entirely on-chip, requiring no external clocking or control, and during steady-state operation would only need to be powered by the injection of constant-amplitude coherent fields.
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