No Arabic abstract
Full-scale quantum computers require the integration of millions of quantum bits. The promise of leveraging industrial semiconductor manufacturing to meet this requirement has fueled the pursuit of quantum computing in silicon quantum dots. However, to date, their fabrication has relied on electron-beam lithography and, with few exceptions, on academic style lift-off processes. Although these fabrication techniques offer process flexibility, they suffer from low yield and poor uniformity. An important question is whether the processing conditions developed in the manufacturing fab environment to enable high yield, throughput, and uniformity of transistors are suitable for quantum dot arrays and do not compromise the delicate qubit properties. Here, we demonstrate quantum dots hosted at a 28Si/28SiO2 interface, fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. As a result, we achieve nanoscale gate patterns with remarkable homogeneity. The quantum dots are well-behaved in the multi-electron regime, with excellent tunnel barrier control, a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance reveals relaxation times of over 1 s at 1 Tesla and coherence times of over 3 ms, matching the quality of silicon spin qubits reported to date. The feasibility of high-quality qubits made with fully-industrial techniques strongly enhances the prospects of a large-scale quantum computer
In recent years semiconducting qubits have undergone a remarkable evolution, making great strides in overcoming decoherence as well as in prospects for scalability, and have become one of the leading contenders for the development of large-scale quantum circuits. In this Review we describe the current state of the art in semiconductor charge and spin qubits based on gate-controlled semiconductor quantum dots, shallow dopants, and color centers in wide band gap materials. We frame the relative strengths of the different semiconductor qubit implementations in the context of quantum simulations, computing, sensing and networks. By highlighting the status and future perspectives of the basic types of semiconductor qubits, this Review aims to serve as a technical introduction for non-specialists as well as a forward-looking reference for scientists intending to work in this field.
We demonstrate a 12 quantum dot device fabricated on an undoped Si/SiGe heterostructure as a proof-of-concept for a scalable, linear gate architecture for semiconductor quantum dots. The device consists of 9 quantum dots in a linear array and 3 single quantum dot charge sensors. We show reproducible single quantum dot charging and orbital energies, with standard deviations less than 20% relative to the mean across the 9 dot array. The single quantum dot charge sensors have a charge sensitivity of 8.2 x 10^{-4} e/root(Hz) and allow the investigation of real-time charge dynamics. As a demonstration of the versatility of this device, we use single-shot readout to measure a spin relaxation time T1 = 170 ms at a magnetic field B = 1 T. By reconfiguring the device, we form two capacitively coupled double quantum dots and extract a mutual charging energy of 200 microeV, which indicates that 50 GHz two-qubit gate operation speeds are feasible.
Recent improvements in materials growth and fabrication techniques may finally allow for superconducting semiconductors to realize their potential. Here we build on a recent proposal to construct superconducting devices such as wires, Josephson junctions, and qubits inside and out-of single crystal silicon or germanium. Using atomistic fabrication techniques such as STM hydrogen lithography, heavily-doped superconducting regions within a single crystal could be constructed. We describe the characteristic parameters of basic superconducting elements---a 1D wire and a tunneling Josephson junction---and estimate the values for boron-doped silicon. The epitaxial, single-crystal nature of these devices, along with the extreme flexibility in device design down to the single-atom scale, may enable lower-noise or new types of devices and physics. We consider applications for such super-silicon devices, showing that the state-of-the-art transmon qubit and the sought-after phase-slip qubit can both be realized. The latter qubit leverages the natural high kinetic inductance of these materials. Building on this, we explore how kinetic inductance based particle detectors (e.g., photon or phonon) could be realized with potential application in astronomy or nanomechanics. We discuss super-semi devices (such as in silicon, germanium, or diamond) which would not require atomistic fabrication approaches and could be realized today.
When a system is thermally coupled to only a small part of a larger bath, statistical fluctuations of the temperature (more precisely, the internal energy) of this sub-bath around the mean temperature defined by the larger bath can become significant. We show that these temperature fluctuations generally give rise to 1/f-like noise power spectral density from even a single two-level system. We extend these results to a distribution of fluctuators, finding the corresponding modification to the Dutta-Horn relation. Then we consider the specific situation of charge noise in silicon quantum dot qubits and show that recent experimental data [E. J. Connors, et al., Phys. Rev. B 100, 165305 (2019)] can be modeled as arising from as few as two two-level fluctuators, and accounting for sub-bath size improves the quality of the fit.
We propose and study a realistic model for the decoherence of topological qubits, based on Majorana fermions in one-dimensional topological superconductors. The source of decoherence is the fluctuating charge on a capacitively coupled gate, modeled by non-interacting electrons. In this context, we clarify the role of quantum fluctuations and thermal fluctuations and find that quantum fluctuations do not lead to decoherence, while thermal fluctuations do. We explicitly calculate decay times due to thermal noise and give conditions for the gap size in the topological superconductor and the gate temperature. Based on this result, we provide simple rules for gate geometries and materials optimized for reducing the negative effect of thermal charge fluctuations on the gate.