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Register a new userDevelopment of a Neutron Imaging Sensor using INTPIX4-SOI Pixelated Silicon Devices
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We have developed a neutron imaging sensor based on an INTPIX4-SOI pixelated silicon device. Neutron irradiation tests are performed at several neutron facilities to investigate sensors responses for neutrons. Detection efficiency is measured to be around $1.5$% for thermal neutrons. Upper bound of spatial resolution is evaluated to be $4.1 pm 0.2 ~mu$m in terms of a standard deviation of the line spread function.
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SOI (Silicon-On-Insulator) pixel sensor is promising technology for developing the high position resolution detector by integrating the small pixels and circuits in the monolithic way. The event driven (trigger mode) SOI based pixel sensor has also been developed for the application of X-ray astronomy with the purpose of reducing the noise using anti-coincidence event. This trigger mode SOI pixel sensor working with in the rate of kilo Hz is also a promising scatter detector for advanced Compton imaging to track the Compton recoiled electrons.
We are developing double silicon-on-insulator (DSOI) pixel sensors for various applications such as for high-energy experiments. The performance of DSOI devices has been evaluated including total ionization damage (TID) effect compensation in transistors using a test-element-group (TEG) up to 2 MGy and in integration-type sensors up to 100 kGy. In this article, successful TID compensation in a pixel-ASD-readout-circuit is shown up to 100 kGy for the application of DSOI to counting-type sensors. The cross-talk suppression in DSOI is being evaluated. These results encourage us that DSOI sensors are applicable to future high-energy experiments such as the BELLE-II experiment or the ILC experiment.
An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry witch mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.
This paper presents the design of a new monolithic Silicon-On-Insulator pixel sensor in $200~nm$ SOI CMOS technology. The main application of the proposed pixel detector is the spectroscopy, but it can also be used for the minimum ionizing particle (MIP) tracking in particle physics experiments. For this reason few differe
Sensors fabricated from high resistivity, float zone, silicon material have been the basis of vertex detectors and trackers for the last 30 years. The areas of these devices have increased from a few square cm to $> 200 m^2$ for the existing CMS tracker. High Luminosity Large Hadron Collider (HL-LHC), CMS and ATLAS tracker upgrades will each require more than $200 m^2$ of silicon and the CMS High Granularity Calorimeter (HGCAL) will require more than $600 m^2$. The cost and complexity of assembly of these devices is related to the area of each module, which in turn is set by the size of the silicon sensors. In addition to large area, the devices must be radiation hard, which requires the use of sensors thinned to 200 microns or less. The combination of wafer thinning and large wafer diameter is a significant technical challenge, and is the subject of this work. We describe work on development of thin sensors on $200 mm$ wafers using wafer bonding technology. Results of development runs with float zone, Silicon-on-Insulator and Silicon-Silicon bonded wafer technologies are reported.
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