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Register a new userHardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques
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Added by
Jianlei Yang
Publication date
2020
fields
Informatics Engineering
and research's language is
English
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Computing-in-memory (CIM) is proposed to alleviate the processor-memory data transfer bottleneck in traditional Von-Neumann architectures, and spintronics-based magnetic memory has demonstrated many facilitation in implementing CIM paradigm. Since hardware security has become one of the major concerns in circuit designs, this paper, for the first time, investigates spin-based computing-in-memory (SpinCIM) from a security perspective. We focus on two fundamental questions: 1) how the new SpinCIM computing paradigm can be exploited to enhance hardware security? 2) what security concerns has this new SpinCIM computing paradigm incurred?
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Hyperdimensional Computing (HDC) is an emerging computational framework that mimics important brain functions by operating over high-dimensional vectors, called hypervectors (HVs). In-memory computing implementations of HDC are desirable since they can significantly reduce data transfer overheads. All existing in-memory HDC platforms consider binary HVs where each dimension is represented with a single bit. However, utilizing multi-bit HVs allows HDC to achieve acceptable accuracies in lower dimensions which in turn leads to higher energy efficiencies. Thus, we propose a highly accurate and efficient multi-bit in-memory HDC inference platform called MIMHD. MIMHD supports multi-bit operations using ferroelectric field-effect transistor (FeFET) crossbar arrays for multiply-and-add and FeFET multi-bit content-addressable memories for associative search. We also introduce a novel hardware-aware retraining framework (HWART) that trains the HDC model to learn to work with MIMHD. For six popular datasets and 4000 dimension HVs, MIMHD using 3-bit (2-bit) precision HVs achieves (i) average accuracies of 92.6% (88.9%) which is 8.5% (4.8%) higher than binary implementations; (ii) 84.1x (78.6x) energy improvement over a GPU, and (iii) 38.4x (34.3x) speedup over a GPU, respectively. The 3-bit $times$ is 4.3x and 13x faster and more energy-efficient than binary HDC accelerators while achieving similar accuracies.
Molecular communication is a new field of communication where molecules are used to transfer information. Among the proposed methods, molecular communication via diffusion (MCvD) is particularly effective. One of the main challenges in MCvD is the intersymbol interference (ISI), which inhibits communication at high data rates. Furthermore, at the nano scale, energy efficiency becomes an essential problem. Before addressing these problems, a pre-determined threshold for the received signal must be calculated to make a decision. In this paper, an analytical technique is proposed to determine the optimum threshold, whereas in the literature, these thresholds are generally calculated empirically. Since the main goal of this paper is to build an MCvD system suitable for operating at high data rates without sacrificing quality, new modulation and filtering techniques are proposed to decrease the effects of ISI and enhance energy efficiency. As a transmitter-based solution, a modulation technique for MCvD, molecular transition shift keying (MTSK), is proposed in order to increase the data rate via suppressing the ISI. Furthermore, for energy efficiency, a power adjustment technique that utilizes the residual molecules is proposed. Finally, as a receiver-based solution, a new energy efficient decision feedback filter (DFF) is proposed as a substitute for the decoders such as minimum mean squared error (MMSE) and decision feedback equalizer (DFE). The error performance of DFF and MMSE equalizers are compared in terms of bit error rates, and it is concluded that DFF may be more advantageous when energy efficiency is concerned, due to its lower computational complexity.
Bayesian inference is an effective approach for solving statistical learning problems, especially with uncertainty and incompleteness. However, Bayesian inference is a computing-intensive task whose efficiency is physically limited by the bottlenecks of conventional computing platforms. In this work, a spintronics based stochastic computing approach is proposed for efficient Bayesian inference. The inherent stochastic switching behaviors of spintronic devices are exploited to build stochastic bitstream generator (SBG) for stochastic computing with hybrid CMOS/MTJ circuits design. Aiming to improve the inference efficiency, an SBG sharing strategy is leveraged to reduce the required SBG array scale by integrating a switch network between SBG array and stochastic computing logic. A device-to-architecture level framework is proposed to evaluate the performance of spintronics based Bayesian inference system (SPINBIS). Experimental results on data fusion applications have shown that SPINBIS could improve the energy efficiency about 12X than MTJ-based approach with 45% design area overhead and about 26X than FPGA-based approach.
Racetrack memories (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. This paper presents data placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime thereby minimizing the number of shifts. We present an integer linear programming (ILP) formulation for optimal data placement in RMs, and revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5%, outperforming the state of the art by up to 16.1%.
Spintronics, the use of spin of an electron instead of its charge, has received huge attention from research communities for different applications including memory, interconnects, logic implementation, neuromorphic computing, and many other applications. Here, in this paper, we review the works within spintronics, more specifically on spin-orbit torque (SOT) within different research groups. We also provide researchers an insight into the future potentials of the SOT-based designs. This comprehensive review paper covers different aspects of SOT-based design from device and circuit to architecture level as well as more ambitious and futuristic applications of such technology.
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