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Register a new userPerformance of a Front End prototype ASIC for picosecond precision time measurements with LGAD sensors
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Added by
Christina Agapopoulou
Publication date
2020
fields
Physics
and research's language is
English
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For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an excellent timing resolution below 50 ps. The front-end read-out ASIC must maintain the performance of the sensor, while keeping low power consumption. This paper presents the results on the first prototype of a front-end ASIC, named ALTIROC0, which contains the analog stages (preamplifier and discriminator) of the read-out chip. The ASIC was characterised both alone and as part of a module with a 2$times$2 LGAD array of 1.1$times$1.1 mm$^2$ pads bump-bonded to it. The various contributions of the electronics to the time resolution were investigated in test-bench measurements with a calibration setup. Both when the ASIC is alone or with a bump-bonded sensor, the jitter of the ASIC is better than 20 ps for an injected charge of 10 fC. The time walk effect that arises from the different response of the preamplifier for various injected charges can be corrected up to 10 ps using a Time Over Threshold measurement. The combined performance of the ASIC and the LGAD sensor, which was measured during a beam test campaign in October 2018 with pions of 120 GeV energy at the CERN SPS, is around 40 ps for all measured modules. All tested modules show good efficiency and time resolution uniformity.
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The High-Granularity Timing Detector is a detector proposed for the ATLAS Phase II upgrade. The detector, based on the Low-Gain Avalanche Detector (LGAD) technology will cover the pseudo-rapidity region of $2.4<|eta|<4.0$ with two end caps on each side and a total area of 6.4 $m^2$. The timing performance can be improved by implanting an internal gain layer that can produce signal with a fast rising edge, which improve significantly the signal-to-noise ratio. The required average timing resolution per track for a minimum-ionising particle is 30 ps at the start and 50 ps at the end of the HL-LHC operation. This is achieved with several layers of LGAD. The innermost region of the detector would accumulate a 1 MeV-neutron equivalent fluence up to $2.5 times 10^{15} cm^{-2}$ before being replaced during the scheduled shutdowns. The addition of this new detector is expected to play an important role in the mitigation of high pile-up at the HL-LHC. The layout and performance of the vario
The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate the performance of the analog frontend, with the goal to achieve 40 to 50 ps time resolution per hit with LGAD (therefore reach about 30ps per track with two detector-layer hits per track). ETROC0 consists of preamplifier and discriminator stages, which amplifies the LGAD signal and generates digital pulses containing time of arrival and time over threshold information. This paper will focus on the design considerations that lead to the ETROC front-end architecture choice, the key design features of the building blocks, the methodology of using the LGAD simulation data to evaluate and optimize the front-end design. The ETROC0 prototype chips have been extensively tested using charge injection and the measured performance agrees well with simulation. The initial beam test results are also presented, with time resolution of around 33 ps observed from the preamplifier waveform analysis and around 41 ps from the discriminator pulses analysis. A subset of ETROC0 chips have also been tested to a total ionizing dose of 100 MRad with X-ray and no performance degradation been observed.
We report on the development of a front-end ASIC for silicon-strip detectors of the J-PARC Muon g-2/EDM experiment. This experiment aims to measure the muon anomalous magnetic moment and electric dipole moment precisely to explore new physics beyond the Standard Model. Since the time and momentum of positrons from muon decay are key information in the experiment, a fast response with high granularity is demanded to silicon-strip detectors as the positron tracker. The readout ASIC is thus required to tolerate a high hit rate of 1.4 MHz per strip and to have deep memory for the period of 40 us with 5 ns time resolution. To satisfy the experimental requirements, an analog prototype ASIC was newly designed with the Silterra 180 nm CMOS technology. In the evaluation test, the time-walk was demonstrated to reach 0.8~ns with a sufficient dynamic range of 6~MIPs and pulse width of 45~ns for 1 MIP event. The design details and performance of the ASIC are discussed in this article.
Compact multi-channel radiation detectors rely on low noise front-end application specific integrated circuits (ASICs) to achieve high spectral resolution. Here, a new ASIC developed to readout virtual Frisch-grid cadmium zinc telluride (VFG CZT) detectors for gamma ray spectroscopy is presented. Corresponding to each ionizing event in the detector, the ASIC measures the amplitude and timing at the anode, the cathode and four pad sense electrodes associated with each sensor in a detector array. The ASIC is comprised of 52 channels of which there are 4 cathode channels and 48 channels which can be configured as either anode channels with a baseline of 250 mV or pad sense channels to process induced signals with a baseline of 1.2 V. With a static power dissipation of 3 mW, each channel performs low-noise charge amplification, high-order shaping, peak and timing detection along with analog storage and multiplexing. The overall channel linearity was better than $pm$ 1 % with timing resolution down to 700 ps for charges greater than 8 fC in the 3 MeV range. With a 4 x 4 array of 6 mm x 6 mm x 20 mm virtual Frisch-grid bar sensors connected and biased, an electronic resolution of $approx$ 270 rms $e^{-}$ for charges up to 100 fC in the 3.2 MeV range was measured. Spectral measurements obtained with the 3D correction technique demonstrated resolutions of 1.8 % FWHM at 238 keV and 0.9 % FWHM at 662 keV.
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also presented in order to demonstrate the potential of the architecture as a reliable front-end readout electronic solution.
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