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Register a new userFATALIC: A novel CMOS front-end readout ASIC for the ATLAS Tile Calorimeter
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Added by
Stylianos Angelidakis
Publication date
2018
fields
Physics
and research's language is
English
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The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also presented in order to demonstrate the potential of the architecture as a reliable front-end readout electronic solution.
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The CALICE collaboration is presently constructing a test hadron calorimeter (HCAL) with 7620 scintillator tiles read out by novel photo-detectors - Silicon Photomultipliers (SiPMs). This prototype is the first device which uses SiPMs on a large scal
e. We present the design of the HCAL and report on measured properties of more than 10 thousand SiPMs. We discuss the SiPM efficiency, gain, cross-talk, and noise rate dependence on bias voltage and temperature, including the spread in these parameters. We analyze the reasons for SiPM rejection and present the results of the long term stability studies. The first measurements of the SiPM radiation hardness are presented. We compare properties of SiPM with the properties of similar devices, MRS APD and MPPC. A possibility to make the tiles thinner and to read them out without WLS fibers has been studied.
Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 um CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $mu$-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the Silterra 180~nm CMOS technology and has 16 readout channels. We carried out the performance test at room temperature and the results showed an equivalent noise charge of 2695$pm$71~e$^-$ (rms) with a detector capacitance of 300~pF. The dynamic range was measured to be 20--100~fC in the low-gain mode and 200--1600~fC in the high-gain mode within 10% integral nonlinearity at room temperature. We also tested the performance at the liquid-Ar temperature and found a deterioration of the noise level with a longer shaper time. Based on these results, we also discuss a unique simulation methodology for future cold-electronics development. This method can be applicable to design the electronics used at low temperature.
The ATLAS hadronic Tile Calorimeter will undergo major upgrades to the on- and off-detector electronics in preparation for the High Luminosity program of the Large Hadron Collider (HL-LHC) in 2026, so that the system can cope with the HL-LHC increased radiation levels and out-of-time pileup. The on-detector electronics of the upgraded system will continuously digitize and transmit all photo-multiplier signals to the off-detector systems at a 40 MHz rate. The off-detector electronics will store the data in pipeline buffers, produce digital hadronic tower sums for the ATLAS Level-0 trigger system, and read out selected events. The modular on-detector electronics feature radiation-tolerant commercial off-the-shelf components and redundant design to minimize single points of failure. The timing, control and communication interface with the off-detector electronics is implemented with modern Field Programmable Gate Arrays and high speed fibre optic links running up to 9.6 Gbps.
We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias on the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.
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