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Register a new userInvestigation of gating effect in Si spin MOSFET
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Authors
Soobeom Lee
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A gate voltage application in a Si-based spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) modulates spin accumulation voltages, where both electrical conductivity and drift velocity are modified while keeping constant electric current. An unprecedented reduction in the spin accumulation voltages in a Si spin MOSFET under negative gate voltage applications is observed in a high electric bias current regime. To support our claim, the electric bias current dependence of the spin accumulation voltage under the gate voltage applications is investigated in detail and compared to a spin drift diffusion model including the conductance mismatch effect. We proved that the drastic decrease of the mobility and spin lifetime in the Si channel is due to the optical phonon emission at the high electric bias current, which consequently reduced the spin accumulation voltage.
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Spin transport in non-degenerate semiconductors is expected to pave a way to the creation of spin transistors, spin logic devices and reconfigurable logic circuits, because room temperature (RT) spin transport in Si has already been achieved. However, RT spin transport has been limited to degenerate Si, which makes it difficult to produce spin-based signals because a gate electric field cannot be used to manipulate such signals. Here, we report the experimental demonstration of spin transport in non-degenerate Si with a spin metal-oxide-semiconductor field-effect transistor (MOSFET) structure. We successfully observed the modulation of the Hanle-type spin precession signals, which is a characteristic spin dynamics in non-degenerate semiconductor. We obtained long spin transport of more than 20 {mu}m and spin rotation, greater than 4{pi} at RT. We also observed gate-induced modulation of spin transport signals at RT. The modulation of spin diffusion length as a function of a gate voltage was successfully observed, which we attributed to the Elliott-Yafet spin relaxation mechanism. These achievements are expected to make avenues to create of practical Si-based spin MOSFETs.
This paper presents a physics-based model for the threshold voltage in bulk MOSFETs valid from room down to cryogenic temperature (4.2 K). The proposed model is derived from Poissons equation including bandgap widening, intrinsic carrier-density scaling, and incomplete ionization. We demonstrate that accounting for incomplete ionization in the expression of the threshold voltage is critical for an accurate estimation of the current. The model is validated with our experimental results from nMOSFETs of a 28-nm CMOS process. The developed model is a key element for a cryo-CMOS compact model and can serve as a guide to optimize processes for high-performance cryo-computing and ultra-low-power quantum computing.
The temperature evolution of spin relaxation time, {tau}sf, in degenerate silicon (Si)-based lateral spin valves is investigated by means of the Hanle effect measurements. {tau}sf at 300 K is estimated to be 1.68+-0.03 ns and monotonically increased with decreasing temperature down to 100 K. Below 100 K, in contrast, it shows almost a constant value of ca. 5 ns. The temperature dependence of the conductivity of the Si channel shows a similar behavior to that of the {tau}sf, i.e., monotonically increasing with decreasing temperature down to 100 K and a weak temperature dependence below 100 K. The temperature evolution of conductivity reveals that electron scattering due to magnetic impurities is negligible. A comparison between {tau}sf and momentum scattering time reveals that the dominant spin scattering mechanism in the Si is the Elliott-Yafet mechanism, and the ratio of the momentum scattering time to the {tau}sf attributed to nonmagnetic impurities is approximately 3.77*10^-6, which is more than two orders of magnitude smaller than that of copper.
Positive magnetoresistance (PMR) of a silicon MOSFET in parallel magnetic fields B has been measured at high electron densities n >> n_c where n_c is the critical density of the metal-insulator transition (MIT). It turns out that the normalized PMR curves, R(B)/R(0), merge together when the field is scaled according to B/B_c(n) where B_c is the field in which electrons become fully spin polarized. The values of B_c have been calculated from the simple equality between the Zeeman splitting energy and the Fermi energy taking into account the experimentally measured dependence of the spin susceptibility on the electron density. This extends the range of validity of the scaling all the way to a deeply metallic regime far away from MIT. The subsequent analysis of PMR for low n >~ n_c demonstrated that the merging of the initial parts of curves can bee achieved only with taking into account the temperature dependence of B_c. It is also shown that the shape of the PMR curves at strong magnetic fields is affected by a crossover from a purely two-dimensional (2D) electron transport to a regime where out-of-plane carrier motion becomes important (quasi-three-dimensional regime).
A novel method for extracting threshold voltage and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion is presented. This generalized constant-current (GCC) method exploits the charge-based model of MOSFETs to extract threshold voltage and other substrate-effect related parameters. The method is applicable over a wide range of current throughout weak and moderate inversion and to some extent in strong inversion. This method is particularly useful when applied for MOSFETs presenting edge conduction effect (subthreshold hump) in CMOS processes using Shallow Trench Isolation (STI).
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