Subscribe to the gold package and get unlimited access to Shamra Academy
Register a new userSystem-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips
238
0
0.0
(
0
)
Added by
Jan Moritz Joseph
Publication date
2019
fields
Informatics Engineering
and research's language is
English
Ask ChatGPT about the research
No Arabic abstract
For a system-level design of Networks-on-Chip for 3D heterogeneous System-on-Chip (SoC), the locations of components, routers and vertical links are determined from an application model and technology parameters. In conventional methods, the two inputs are accounted for separately; here, we define an integrated problem that considers both application model and technology parameters. We show that this problem does not allow for exact solution in reasonable time, as common for many design problems. Therefore, we contribute a heuristic by proposing design steps, which are based on separation of intralayer and interlayer communication. The advantage is that this new problem can be solved with well-known methods. We use 3D Vision SoC case studies to quantify the advantages and the practical usability of the proposed optimization approach. We achieve up to 18.8% reduced white space and up to 12.4% better network performance in comparison to conventional approaches.
rate research
Read More
Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this paper, we propose to synthesize brain-network-inspired interconnections for large-scale network-on-chips. Firstly, we propose a method to generate brain-network-inspired topologies with limited scale-free and power-law small-world properties, which have a low total link length and extremely low average hop count approximately proportional to the logarithm of the network size. In addition, given the large-scale applications and the modular topology, we present an application mapping method, including task mapping and deterministic deadlock-free routing, to minimize the power consumption and hop count. Finally, a cycle-accurate simulator BookSim2 is used to validate the architecture performance with different synthetic traffic patterns and large-scale test cases, including real-world communication networks for the graph processing application. Experiments show that, compared with other topologies and methods, the NoC design generated by the proposed method presents significantly lower average hop count and lower average latency. Especially in graph processing applications with a power-law and tightly coupled inter-core communication, the brain-network-inspired NoC has up to 70% lower average hop count and 75% lower average latency than mesh-based NoCs.
The Network-on-Chips is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this work, we consider the generalized fault-tolerance topology generation problem, where the link or switch failures can happen, for application-specific network-on-chips (ASNoC). With a user-defined number, K, we propose an integer linear programming (ILP) based method to generate ASNoC topologies, which can tolerate at most K faults in switches or links. Given the communication requirements between cores and their floorplan, we first propose a convex-cost-flow based method to solve a core mapping problem for building connections between the cores and switches. Second, an ILP based method is proposed to allocate K+1 switch-disjoint routing paths for every communication flow between the cores. Finally, to reduce switch sizes, we propose sharing the switch ports for the connections between the cores and switches and formulate the port sharing problem as a clique-partitioning problem Additionally, we propose an ILP-based method to simultaneously solve the core mapping and routing path allocation problems when considering physical link failures only. Experimental results show that the power consumptions of fault-tolerance topologies increase almost linearly with K because of the routing path redundancy. When both switch faults and link faults are considered, port sharing can reduce the average power consumption of fault-tolerance topologies with K = 1, K = 2 and K = 3 by 18.08%, 28.88%, and 34.20%, respectively. When considering only the physical link faults, the experimental results show that compared to the FTTG algorithm, the proposed method reduces power consumption and hop count by 10.58% and 6.25%, respectively; compared to the DBG based method, the proposed method reduces power consumption and hop count by 21.72% and 9.35%, respectively.
Linear models are regularly used for mapping cores to tiles in a chip. System-on-Chip (SoC) design requires integration of functional units with varying sizes, but conventional models only account for identical-sized cores. Linear models cannot calculate the varying areas of cores in SoCs directly and must rely on approximations. We propose using non-linear models: Semi-definite programming (SDP) allows easy model definitions and achieves approximately 20% reduced area and up to 80% reduced white space. As computational time is similar to linear models, they can be applied, practically.
3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moores law scaling. 3D stacking promises potential gains in performance, power and cost but the actual magnitude of gains varies depending on end-application, technology choices and design. In this talk, we will discuss some key challenges associated with 3D design and how design-for-3D will require us to break traditional silos of micro-architecture, circuit/physical design and manufacturing technology to work across abstractions to enable the gains promised by 3D technologies.
In the last years, it was demonstrated that neutral molecules can be loaded on a microchip directly from a supersonic beam. The molecules are confined in microscopic traps that can be moved smoothly over the surface of the chip. Once the molecules are trapped, they can be decelerated to a standstill, for instance, or pumped into selected quantum states by laser light or microwaves. Molecules are detected on the chip by time-resolved spatial imaging, which allows for the study of the distribution in the phase space of the molecular ensemble.
Log in to be able to interact and post comments
comments
Fetching comments
Sign in to be able to follow your search criteria
