No Arabic abstract
Photonic quantum computing is one of the leading approaches to universal quantum computation. However, large-scale implementation of photonic quantum computing has been hindered by its intrinsic difficulties, such as probabilistic entangling gates for photonic qubits and lack of scalable ways to build photonic circuits. Here we discuss how to overcome these limitations by taking advantage of two key ideas which have recently emerged. One is a hybrid qubit-continuous variable approach for realizing a deterministic universal gate set for photonic qubits. The other is time-domain multiplexing technique to perform arbitrarily large-scale quantum computing without changing the configuration of photonic circuits. These ideas together will enable scalable implementation of universal photonic quantum computers in which hardware-efficient error correcting codes can be incorporated. Furthermore, all-optical implementation of such systems can increase the operational bandwidth beyond THz in principle, utimately enabling large-scale fault-tolerant universal quantum computers with ultra-high operation frequency.
Considering the large-scale quantum computer, it is important to know how much quantum computational resources is necessary precisely and quickly. Unfortunately the previous methods so far cannot support a large-scale quantum computing practically and therefore the analysis because they usually use a non-structured code. To overcome this problem, we propose a fast mapping by using the hierarchical assembly code which is much more compact than the non-structured code. During the mapping process, the necessary modules and their interconnection can be dynamically mapped by using the communication bus at the cost of additional qubits. In our study, the proposed method works very fast such as 1 hour than 1500 days for Shor algorithm to factorize 512-bit integer. Meanwhile, since the hierarchical assembly code has high degree of locality, it has shorter SWAP chains and hence it does not increase the quantum computation time than expected.
Certain physical systems that one might consider for fault-tolerant quantum computing where qubits do not readily interact, for instance photons, are better suited for measurement-based quantum-computational protocols. Here we propose a measurement-based model for universal quantum computation that simulates the braiding and fusion of Majorana modes. To derive our model we develop a general framework that maps any scheme of fault-tolerant quantum computation with stabilizer codes into the measurement-based picture. As such, our framework gives an explicit way of producing fault-tolerant models of universal quantum computation with linear optics using protocols developed using the stabilizer formalism. Given the remarkable fault-tolerant properties that Majorana modes promise, the main example we present offers a robust and resource efficient proposal for photonic quantum computation.
Photonics is the platform of choice to build a modular, easy-to-network quantum computer operating at room temperature. However, no concrete architecture has been presented so far that exploits both the advantages of qubits encoded into states of light and the modern tools for their generation. Here we propose such a design for a scalable and fault-tolerant photonic quantum computer informed by the latest developments in theory and technology. Central to our architecture is the generation and manipulation of three-dimensional hybrid resource states comprising both bosonic qubits and squeezed vacuum states. The proposal enables exploiting state-of-the-art procedures for the non-deterministic generation of bosonic qubits combined with the strengths of continuous-variable quantum computation, namely the implementation of Clifford gates using easy-to-generate squeezed states. Moreover, the architecture is based on two-dimensional integrated photonic chips used to produce a qubit cluster state in one temporal and two spatial dimensions. By reducing the experimental challenges as compared to existing architectures and by enabling room-temperature quantum computation, our design opens the door to scalable fabrication and operation, which may allow photonics to leap-frog other platforms on the path to a quantum computer with millions of qubits.
We analyze the latency of fault-tolerant quantum computing based on the 9-qubit Bacon-Shor code using a local, two-dimensional architecture. We embed the data qubits in a 7 by 7 array of physical qubits, where the extra qubits are used for ancilla preparation and qubit transportation by means of a SWAP chain. The latency is reduced with respect to a similar implementation using Steanes 7-qubit code (K. M. Svore, D. P. DiVincenzo, and B. M. Terhal, Quantum Information & Computation {bf 7}, 297 (2007)). Furthermore, the error threshold is also improved to $2.02 times 10^{-5}$, when memory errors are taken to be one tenth of the gate error rates.
Quantum computation promises significant computational advantages over classical computation for some problems. However, quantum hardware suffers from much higher error rates than in classical hardware. As a result, extensive quantum error correction is required to execute a useful quantum algorithm. The decoder is a key component of the error correction scheme whose role is to identify errors faster than they accumulate in the quantum computer and that must be implemented with minimum hardware resources in order to scale to the regime of practical applications. In this work, we consider surface code error correction, which is the most popular family of error correcting codes for quantum computing, and we design a decoder micro-architecture for the Union-Find decoding algorithm. We propose a three-stage fully pipelined hardware implementation of the decoder that significantly speeds up the decoder. Then, we optimize the amount of decoding hardware required to perform error correction simultaneously over all the logical qubits of the quantum computer. By sharing resources between logical qubits, we obtain a 67% reduction of the number of hardware units and the memory capacity is reduced by 70%. Moreover, we reduce the bandwidth required for the decoding process by a factor at least 30x using low-overhead compression algorithms. Finally, we provide numerical evidence that our optimized micro-architecture can be executed fast enough to correct errors in a quantum computer.