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Register a new userHierarchical System Mapping for Large-Scale Fault-Tolerant Quantum Computing
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Considering the large-scale quantum computer, it is important to know how much quantum computational resources is necessary precisely and quickly. Unfortunately the previous methods so far cannot support a large-scale quantum computing practically and therefore the analysis because they usually use a non-structured code. To overcome this problem, we propose a fast mapping by using the hierarchical assembly code which is much more compact than the non-structured code. During the mapping process, the necessary modules and their interconnection can be dynamically mapped by using the communication bus at the cost of additional qubits. In our study, the proposed method works very fast such as 1 hour than 1500 days for Shor algorithm to factorize 512-bit integer. Meanwhile, since the hierarchical assembly code has high degree of locality, it has shorter SWAP chains and hence it does not increase the quantum computation time than expected.
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Photonic quantum computing is one of the leading approaches to universal quantum computation. However, large-scale implementation of photonic quantum computing has been hindered by its intrinsic difficulties, such as probabilistic entangling gates for photonic qubits and lack of scalable ways to build photonic circuits. Here we discuss how to overcome these limitations by taking advantage of two key ideas which have recently emerged. One is a hybrid qubit-continuous variable approach for realizing a deterministic universal gate set for photonic qubits. The other is time-domain multiplexing technique to perform arbitrarily large-scale quantum computing without changing the configuration of photonic circuits. These ideas together will enable scalable implementation of universal photonic quantum computers in which hardware-efficient error correcting codes can be incorporated. Furthermore, all-optical implementation of such systems can increase the operational bandwidth beyond THz in principle, utimately enabling large-scale fault-tolerant universal quantum computers with ultra-high operation frequency.
Quantum computation promises significant computational advantages over classical computation for some problems. However, quantum hardware suffers from much higher error rates than in classical hardware. As a result, extensive quantum error correction is required to execute a useful quantum algorithm. The decoder is a key component of the error correction scheme whose role is to identify errors faster than they accumulate in the quantum computer and that must be implemented with minimum hardware resources in order to scale to the regime of practical applications. In this work, we consider surface code error correction, which is the most popular family of error correcting codes for quantum computing, and we design a decoder micro-architecture for the Union-Find decoding algorithm. We propose a three-stage fully pipelined hardware implementation of the decoder that significantly speeds up the decoder. Then, we optimize the amount of decoding hardware required to perform error correction simultaneously over all the logical qubits of the quantum computer. By sharing resources between logical qubits, we obtain a 67% reduction of the number of hardware units and the memory capacity is reduced by 70%. Moreover, we reduce the bandwidth required for the decoding process by a factor at least 30x using low-overhead compression algorithms. Finally, we provide numerical evidence that our optimized micro-architecture can be executed fast enough to correct errors in a quantum computer.
To bridge the gap between limited hardware access and the huge demand for experiments for Noisy Intermediate-Scale Quantum (NISQ) computing system study, a simulator which can capture the modeling of both the quantum processor and its classical control system to realize early-stage evaluation and design space exploration, is naturally invoked but still missing. This paper presents SANQ, a Simulation framework for Architecting NISQ computing system. SANQ consists of two components, 1) an optimized noisy quantum computing (QC) simulator with flexible error modeling accelerated by eliminating redundant computation, and 2) an architectural simulation infrastructure to construct behavior models for evaluating the control systems. SANQ is validated with existing NISQ quantum processor and control systems to ensure simulation accuracy. It can capture the variance on the QC device and simulate the timing behavior precisely (<1% and 10% error for various real control systems). Several potential applications are proposed to show that SANQ could benefit the future design of NISQ compiler, architecture, etc.
We analyze the latency of fault-tolerant quantum computing based on the 9-qubit Bacon-Shor code using a local, two-dimensional architecture. We embed the data qubits in a 7 by 7 array of physical qubits, where the extra qubits are used for ancilla preparation and qubit transportation by means of a SWAP chain. The latency is reduced with respect to a similar implementation using Steanes 7-qubit code (K. M. Svore, D. P. DiVincenzo, and B. M. Terhal, Quantum Information & Computation {bf 7}, 297 (2007)). Furthermore, the error threshold is also improved to $2.02 times 10^{-5}$, when memory errors are taken to be one tenth of the gate error rates.
We present a layered hybrid-system approach to quantum communication that involves the distribution of a topological cluster state throughout a quantum network. Photon loss and other errors are suppressed by optical multiplexing and entanglement purification. The scheme is scalable to large distances, achieving an end-to-end rate of 1 kHz with around 50 qubits per node. We suggest a potentially suitable implementation of an individual node composed of erbium spins (single atom or ensemble) coupled via flux qubits to a microwave resonator, allowing for deterministic local gates, stable quantum memories, and emission of photons in the telecom regime.
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