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Register a new userThe High Voltage distribution system of the ATLAS Tile Calorimeter and its performance during data taking
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D. Calvet
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This article documents the characteristics of the high voltage (HV) system of the hadronic calorimeter TileCal of the ATLAS experiment. Such a system is suitable to supply reliable power distribution into particles physics detectors using a large number of PhotoMultiplier Tubes (PMTs). Measurements performed during the 2015 and 2016 data taking periods of the ATLAS detector show that its performance, in terms of stability and noise, fits the specifications. In particular, almost all the PMTs show a voltage instability smaller than 0.5 V corresponding to a gain stability better than 0.5%. A small amount of channels was found not working correctly. To diagnose the origin of such defects, the results of the HV measurements were compared to those obtained using a Laser system. The analysis shows that less than 0.2% of the about 10 thousand HV channels were malfunctioning.
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The ATLAS hadronic Tile Calorimeter will undergo major upgrades to the on- and off-detector electronics in preparation for the High Luminosity program of the Large Hadron Collider (HL-LHC) in 2026, so that the system can cope with the HL-LHC increased radiation levels and out-of-time pileup. The on-detector electronics of the upgraded system will continuously digitize and transmit all photo-multiplier signals to the off-detector systems at a 40 MHz rate. The off-detector electronics will store the data in pipeline buffers, produce digital hadronic tower sums for the ATLAS Level-0 trigger system, and read out selected events. The modular on-detector electronics feature radiation-tolerant commercial off-the-shelf components and redundant design to minimize single points of failure. The timing, control and communication interface with the off-detector electronics is implemented with modern Field Programmable Gate Arrays and high speed fibre optic links running up to 9.6 Gbps.
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also presented in order to demonstrate the potential of the architecture as a reliable front-end readout electronic solution.
This article describes the design, construction and use of a calibration and monitoring system, based on movable 137Cs gamma-ray sources, for the ATLAS Tile Calorimeter (TileCal). The sources, propelled by a water-based liquid through tubes that traverse all the calorimeters cells, produce signals that precisely characterise the response of each tile, thereby providing very granular and accurate data on the response of TileCal to particles. The system has been used to guide and control the quality of the optical instrumentation of all TileCal modules, to set and equalise the dynamic range of the response to physics data, and to set the energy scale of the readout system. In the ATLAS cavern, periodic measurements of the whole detectors response to 137Cs sources allow monitoring the uniformity and stability of all the calorimeters cells as well as maintaining precise knowledge of its energy calibration. The design of the source hydraulic drive systems hardware and software, the data acquisition system and the data processing algorithms are described. Finally, the results of this two-decade program are shown.
The ATLAS trigger has been used very successfully to collect collision data during 2009 and 2010 LHC running at centre of mass energies of 900 GeV, 2.36 TeV, and 7 TeV. This paper presents the ongoing work to commission the ATLAS trigger with proton collisions, including an overview of the performance of the trigger based on extensive online running. We describe how the trigger has evolved with increasing LHC luminosity and give a brief overview of plans for forthcoming LHC running.
To cope with the enhanced luminosity at the Large Hadron Collider (LHC) in 2021, the ATLAS collaboration is planning a major detector upgrade. As a part of this, the Level 1 trigger based on calorimeter data will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEX), which each reconstruct different physics objects for the trigger selection. The jet FEX (jFEX) system is conceived to provide jet identification (including large area jets) and measurements of global variables within a latency budget of less then 400ns. It consists of 6 modules. A single jFEX module is an ATCA board with 4 large FPGAs of the Xilinx Ultrascale+ family, that can digest a total input data rate of ~3.6 Tb/s using up to 120 Multi Gigabit Transceiver (MGT), 24 electrical optical devices, board control and power on the mezzanines to allow flexibility in upgrading controls functions and components without affecting the main board. The 24-layers stack-up was carefully designed to preserve the signal integrity in a very densely populated high speed signal board selecting MEGTRON6 as the most suitable PCB material. This contribution reports on the design challenges and the test results of the jFEX prototypes. In particular the fully assembled final prototype has been tested up to 12.8 Gb/s in house and in integrated tests at CERN. The full jFEX system will be produced by the end of 2018 to allow for installation and commissioning to be completed before LHC restarts in March 2021.
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