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Low-field magnetotransport in graphene cavity devices

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 Added by Hongqi Xu Professor
 Publication date 2018
  fields Physics
and research's language is English




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Confinement and edge structures are known to play significant roles in electronic and transport properties of two-dimensional materials. Here, we report on low-temperature magnetotransport measurements of lithographically patterned graphene cavity nanodevices. It is found that the evolution of the low-field magnetoconductance characteristics with varying carrier density exhibits different behaviors in graphene cavity and bulk graphene devices. In the graphene cavity devices, we have observed that intravalley scattering becomes dominant as the Fermi level gets close to the Dirac point. We associate this enhanced intravalley scattering to the effect of charge inhomogeneities and edge disorder in the confined graphene nanostructures. We have also observed that the dephasing rate of carriers in the cavity devices follows a parabolic temperature dependence, indicating that the direct Coulomb interaction scattering mechanism governs the dephasing at low temperatures. Our results demonstrate the importance of confinement in carrier transport in graphene nanostructure devices.

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The extremely high carrier mobility and the unique band structure, make graphene very useful for field-effect transistor applications. According to several works, the primary limitation to graphene based transistor performance is not related to the material quality, but to extrinsic factors that affect the electronic transport properties. One of the most important parasitic element is the contact resistance appearing between graphene and the metal electrodes functioning as the source and the drain. Ohmic contacts to graphene, with low contact resistances, are necessary for injection and extraction of majority charge carriers to prevent transistor parameter fluctuations caused by variations of the contact resistance. The International Technology Roadmap for Semiconductors, toward integration and down-scaling of graphene electronic devices, identifies as a challenge the development of a CMOS compatible process that enables reproducible formation of low contact resistance. However, the contact resistance is still not well understood despite it is a crucial barrier towards further improvements. In this paper, we review the experimental and theoretical activity that in the last decade has been focusing on the reduction of the contact resistance in graphene transistors. We will summarize the specific properties of graphene-metal contacts with particular attention to the nature of metals, impact of fabrication process, Fermi level pinning, interface modifications induced through surface processes, charge transport mechanism, and edge contact formation.
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