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Register a new userSide-gate leakage and field emission in all-graphene field effect transistors on SiO2/Si substrate
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Added by
Antonio Di Bartolomeo
Publication date
2016
fields
Physics
and research's language is
English
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We fabricate planar all-graphene field-effect transistors with self-aligned side-gates at 100 nm from the main graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO2/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO2 up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at high voltages. We report a field-emission current density as high as 1uA/um between graphene flakes. These findings are essential for the miniaturization of atomically thin devices.
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We study the contact resistance and the transfer characteristics of back-gated field effect transistors of mono- and bi-layer graphene. We measure specific contact resistivity of ~7kohm*um2 and ~30kohm*um2 for Ni and Ti, respectively. We show that the contact resistance is a significant contributor to the total source-to-drain resistance and it is modulated by the back-gate voltage. We measure transfer characteristics showing double dip feature that we explain as the effect of doping due to charge transfer from the contacts causing minimum density of states for graphene under the contacts and in the channel at different gate voltage.
The spin field effect transistor envisioned by Datta and Das opens a gateway to spin information processing. Although the coherent manipulation of electron spins in semiconductors is now possible, the realization of a functional spin field effect transistor for information processing has yet to be achieved, owing to several fundamental challenges such as the low spin-injection efficiency due to resistance mismatch, spin relaxation, and the spread of spin precession angles. Alternative spin transistor designs have therefore been proposed, but these differ from the field effect transistor concept and require the use of optical or magnetic elements, which pose difficulties for the incorporation into integrated circuits. Here, we present an all-electric and all-semiconductor spin field effect transistor, in which these obstacles are overcome by employing two quantum point contacts as spin injectors and detectors. Distinct engineering architectures of spin-orbit coupling are exploited for the quantum point contacts and the central semiconductor channel to achieve complete control of the electron spins -- spin injection, manipulation, and detection -- in a purely electrical manner. Such a device is compatible with large-scale integration and hold promise for future spintronic devices for information processing.
Three types of first generation epitaxial graphene field effect transistors (FET) are presented and their relative merits are discussed. Graphene is epitaxially grown on both the carbon and silicon faces of hexagonal silicon carbide and patterned with electron beam lithography. The channels have a Hall bar geometry to facilitate magnetoresistance measurements. FETs patterned on the Si-face exhibit off-to-on channel resistance ratios that exceed 30. C-face FETs have lower off-to-on resistance ratios, but their mobilities (up to 5000 cm2/Vs) are much larger than that for Si-face transistors. Initial investigations into all-graphene side gate FET structures are promising.
We present an atomistic three-dimensional simulation of graphene nanoribbon field effect transistors (GNR-FETs), based on the self-consistent solution of the 3D Poisson and Schroedinger equation with open boundary conditions within the non-equilibrium Greens Function formalism and a tight-binding hamiltonian. With respect to carbon nanotube FETs, GNR-FETs exhibit comparable performance, reduced sensitivity on the variability of channel chirality, and similar leakage problems due to band-to-band tunneling. Acceptable transistor performance requires effective nanoribbon width of 1-2 nm, that could be obtained with periodic etching patterns or stress patterns.
With the motivation of improving the performance and reliability of aggressively scaled nano-patterned graphene field-effect transistors, we present the first systematic experimental study on charge and current distribution in multilayer graphene field-effect transistors. We find a very particular thickness dependence for Ion, Ioff, and the Ion/Ioff ratio, and propose a resistor network model including screening and interlayer coupling to explain the experimental findings. In particular, our model does not invoke modification of the linear energy-band structure of graphene for the multilayer case. Noise reduction in nano-scale few-layer graphene transistors is experimentally demonstrated and can be understood within this model as well.
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