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Register a new userOverlapped List Successive Cancellation Approach for Hardware Efficient Polar Code Decoder
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Added by
Tiben Che
Publication date
2015
fields
Informatics Engineering
and research's language is
English
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This paper presents an efficient hardware design approach for list successive cancellation (LSC) decoding of polar codes. By applying path-overlapping scheme, the l instances of (l > 1) successive cancellation (SC) decoder for LSC with list size l can be cut down to only one. This results in a dramatic reduction of the hardware complexity without any decoding performance loss. We also develop novel approaches to reduce the latencyassociated with the pipeline scheme. Simulation results show that with proposed design approach the hardware efficiency is increased significantly over the recently proposed LSC decoders.
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Polar codes, discovered by Ar{i}kan, are the first error-correcting codes with an explicit construction to provably achieve channel capacity, asymptotically. However, their error-correction performance at finite lengths tends to be lower than existing capacity-approaching schemes. Using the successive-cancellation algorithm, polar decoders can be designed for very long codes, with low hardware complexity, leveraging the regular structure of such codes. We present an architecture and an implementation of a scalable hardware decoder based on this algorithm. This design is shown to scale to code lengths of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by the amount of available SRAM.
This paper presents a hardware architecture of fast simplified successive cancellation (fast-SSC) algorithm for polar codes, which significantly reduces the decoding latency and dramatically increases the throughput. Algorithmically, fast-SSC algorithm suffers from the fact that its decoder scheduling and the consequent architecture depends on the code rate; this is a challenge for rate-compatible system. However, by exploiting the homogeneousness between the decoding processes of fast constituent polar codes and regular polar codes, the presented design is compatible with any rate. The scheduling plan and the intendedly designed process core are also described. Results show that, compared with the state-of-art decoder, proposed design can achieve at least 60% latency reduction for the codes with length N = 1024. By using Nangate FreePDK 45nm process, proposed design can reach throughput up to 5.81 Gbps and 2.01 Gbps for (1024, 870) and (1024, 512) polar code, respectively.
This work identifies information-theoretic quantities that are closely related to the required list size for successive cancellation list (SCL) decoding to implement maximum-likelihood decoding. It also provides an approximation for these quantities that can be computed efficiently for very long codes. There is a concentration around the mean of the logarithm of the required list size for sufficiently large block lengths. We further provide a simple method to estimate the mean via density evolution for the binary erasure channel (BEC). Simulation results for the binary-input additive white Gaussian noise channel as well as the BEC demonstrate the accuracy of the mean estimate. A modified Reed-Muller code with dynamic frozen bits performs very close to the random coding union (RCU) bound down to the block error rate of $10^{-5}$ under SCL decoding with list size $L=128$ when the block length is $N=128$. The analysis shows how to modify the design to improve the performance when a more practical list size, e.g., $L=32$, is adopted while keeping the performance with $L=128$ unchanged. For the block length of $N=512$, a design performing within $0.4$ dB from the RCU bound down to the block error rate of $10^{-6}$ under an SCL decoder with list size $L=1024$ is provided. The design is modified using the new guidelines so that the performance improves with practical list sizes, e.g., $Lin{8,32,128}$, outperforming 5G designs.
Polar codes are a class of channel capacity achieving codes that has been selected for the next generation of wireless communication standards. Successive-cancellation (SC) is the first proposed decoding algorithm, suffering from mediocre error-correction performance at moderate code length. In order to improve the error-correction performance of SC, two approaches are available: (i) SC-List decoding which keeps a list of candidates by running a number of SC decoders in parallel, thus increasing the implementation complexity, and (ii) SC-Flip decoding that relies on a single SC module, and keeps the computational complexity close to SC. In this work, we propose the partitioned SC-Flip (PSCF) decoding algorithm, which outperforms SC-Flip in terms of error-correction performance and average computational complexity, leading to higher throughput and reduced energy consumption per codeword. We also introduce a partitioning scheme that best suits our PSCF decoder. Simulation results show that at equivalent frame error rate, PSCF has up to $5 times$ less computational complexity than the SC-Flip decoder. At equivalent average number of iterations, the error-correction performance of PSCF outperforms SC-Flip by up to $0.15$ dB at frame error rate of $10^{-3}$.
By constructing chemical reaction networks (CRNs), this paper proposes a method of synthesizing polar decoder using belief propagation (BP) algorithm and successive cancellation (SC) algorithm, respectively. Theoretical analysis and simulation results have validated the feasibility of the method. Reactions in the proposed design could be experimentally implemented with DNA strand displacement reactions, making the proposed polar decoders promising for wide application in nanoscale devices.
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