We electrically measure intrinsic silicon quantum dots with electrostatically defined tunnel barriers. The presence of both p-type and n-type ohmic contacts enables the accumulation of either electrons or holes. Thus we are able to study both transport regimes within the same device. We investigate the effect of the tunnel barriers and the electrostatically defined quantum dots. There is greater localisation of charge states under the tunnel barriers in the case of hole conduction leading to higher charge noise in the p-regime.
In this Report we show the role of charge defects in the context of the formation of electrostatically defined quantum dots. We introduce a barrier array structure to probe defects at multiple locations in a single device. We measure samples both before and after an annealing process which uses an Al$_2$O$_3$ overlayer, grown by atomic layer deposition. After passivation of the majority of charge defects with annealing we can electrostatically define hole quantum dots up to 180 nm in length. Our ambipolar structures reveal amphoteric charge defects that remain after annealing with charging energies of ~10 meV in both the positive and negative charge state.
We present a systematic study of various ways (top gates, local doping, substrate bias) to fabricate and tune multi-dot structures in silicon nanowire multigate MOSFETs (metal-oxide-semiconductor field-effect transistors). The carrier concentration profile of the silicon nanowire is a key parameter to control the formation of tunnel barriers and single-electron islands. It is determined both by the doping profile of the nanowire and by the voltages applied to the top gates and to the substrate. Local doping is achieved with the realisation of up to two arsenic implantation steps in combination with gates and nitride spacers acting as a mask. We compare nominally identical devices with different implantations and different voltages applied to the substrate, leading to the realisation of both intrinsic and doped coupled dot structures. We demonstrate devices in which all the tunnel resistances towards the electrodes and between the dots can be independently tuned with the control top gates wrapping the silicon nanowire.
RF reflectometry offers a fast and sensitive method for charge sensing and spin readout in gated quantum dots. We focus in this work on the implementation of RF readout in accumulation-mode gate-defined quantum dots, where the large parasitic capacitance poses a challenge. We describe and test two methods for mitigating the effect of the parasitic capacitance, one by on-chip modifications and a second by off-chip changes. We demonstrate that these methods enable high-performance charge readout in Si/SiGe quantum dots, achieving a fidelity of 99.9% for a measurement time of 1 $mu$s.
Reliable detection of single electron tunneling in quantum dots (QD) is paramount to use this category of device for quantum information processing. Here, we report charge sensing in a degenerately phosphorus-doped silicon QD by means of a capacitively coupled single-electron tunneling device made of the same material. Besides accurate counting of tunneling events in the QD, we demonstrate that this architecture can be operated to reveal asymmetries in the transport characteristic of the QD. Indeed, the observation of gate voltage shifts in the detectors response as the QD bias is changed is an indication of variable tunneling rates.
We present a novel reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consist of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.