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Register a new userR&D for a Dedicated Fast Timing Layer in the CMS Endcap Upgrade
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Added by
Sebastian White Phd
Publication date
2014
fields
Physics
and research's language is
English
Authors
Sebastian N. White
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The PhaseII Upgrades of CMS are being planned for the High Luminosity LHC (HL-LHC) era when the mean number of interactions per beam crossing (in-time pileup) is expected to reach ~140-200. The potential backgrounds arising from mis-associated jets and photon showers, for example, during event reconstruction could be reduced if physics objects are tagged with an event time. This tag is fully complementary to the event vertex which is already commonly used to reduce mis-reconstruction. Since the tracking vertex resolution is typically ~10^{-3} (50 micron/4.8cm) of the rms vertex distribution, whereas only ~10^{-1} (i.e. 20 vs.170 picoseconds (psec)) is demonstrated for timing, it is often assumed that only photon (i.e. EM calorimeter or shower-max) timing is of interest. We show that the optimal solution will likely be a single timing layer which measures both charged particle and photon time (a pre-shower layer).
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We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16x16 pixel matrix.
We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 W for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the Time of Arrival (TOA) and the Time over Threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65 nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 ps and 9.9 ps with and without the nonlinearity correction, respectively. The TDC block consumes 97 W at the hit occupancy of 1%. Over a temperature range from 23 C to 78 C and a power supply voltage range from 1.05 V to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation-tolerance specifications.
The high pseudo-rapidity region of the CMS muon system is covered by Cathode Strip Chambers (CSC) only and lacks redundant coverage despite the fact that it is a challenging region for muons in terms of backgrounds and momentum resolution. In order to maintain good efficiency for the muon trigger in this region additional RPCs are planned to be installed in the two outermost stations at low angle named RE3/1 and RE4/1. These stations will use RPCs with finer granularity and good timing resolution to mitigate background effects and to increase the redundancy of the system.
We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16x16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminators leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifiers power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. The measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETLs challenging requirements.
The CMS beam and radiation monitoring subsystem BCM1F (Fast Beam Condition Monitor) consists of 8 individual diamond sensors situated around the beam pipe within the pixel detector volume, for the purpose of fast bunch-by-bunch monitoring of beam background and collision products. In addition, effort is ongoing to use BCM1F as an online luminosity monitor. BCM1F will be running whenever there is beam in LHC, and its data acquisition is independent from the data acquisition of the CMS detector, hence it delivers luminosity even when CMS is not taking data. A report is given on the performance of BCM1F during LHC run I, including results of the van der Meer scan and on-line luminosity monitoring done in 2012. In order to match the requirements due to higher luminosity and 25 ns bunch spacing, several changes to the system must be implemented during the upcoming shutdown, including upgraded electronics and precise gain monitoring. First results from Run II preparation are shown.
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