Subscribe to the gold package and get unlimited access to Shamra Academy
Register a new userWafer bonding solution to epitaxial graphene - silicon integration
162
0
0.0
(
0
)
Ask ChatGPT about the research
No Arabic abstract
The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphene nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing.
rate research
Read More
High-performance graphene field-effect transistors have been fabricated on epitaxial graphene synthesized on a two-inch SiC wafer, achieving a cutoff frequency of 100 GHz for a gate length of 240 nm. The high-frequency performance of these epitaxial graphene transistors not only shows the highest speed for any graphene devices up to date, but it also exceeds that of Si MOSFETs at the same gate length. The result confirms the high potential of graphene for advanced electronics applications, marking an important milestone for carbon electronics.
Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain > 1.0 in vacuum (pressure < 2 x 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 inch wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.
A major challenge for the next generation of spintronics devices is the implementation of ferromagnetic-semiconductor thin films as spin injectors and detectors. Spin-polarised carrier injection cannot be accomplished efficiently from metals, and coupled with the rarity of intrinsic ferromagnetic semiconductors this has driven intensive study of diluted magnetic semiconductors. Chief among these is the doped III-V compound (Ga,Mn)As. These materials suffer from a number of drawbacks; they (i) require magnetic-ion doping well above the solubility limit, and (ii) must be hole doped to above the degenerate limit, preventing independent control of the carrier concentration and charge sign. Here we demonstrate the first epitaxial growth of a recently-characterised intrinsic ferromagnetic semiconductor, GdN, on silicon substrates, providing an essential step on the way to integrate new spintronics functionalities into Si-based technology. The films have been characterised as regards their growth toward fully relaxed GdN, the density and mobility of their carriers, and their magnetic behaviour.
Control of the position and density of semiconductor quantum dots (QDs) is vital for a variety of emergent technologies, such as quantum photonics and advanced opto-electronic devices. However, established ordering methods typically call for ex-situ processing prior to growth that have a deleterious impact on the optical quality of nanostructures. Here, we apply a conventional epitaxial growth method - molecular beam epitaxy (MBE) - to achieve wafer scale positioning of optically active QDs with high reproducibility, tunable periodicity, and controlled density across an entire unpatterned 3-inch semiconductor wafer. Hereby, we exploit material thickness gradients across the wafer to modulate the QD nucleation probability and demonstrate how our approaches can be used to achieve strong periodic modulation of the local dot density tunable over length scales ranging from a few millimeters to at least a few hundred microns in one or two spatial directions. The methods are universal and are applicable to a wide variety of semiconductor material systems.
We present a method for low temperature plasma-activated direct wafer bonding of III-V materials to Si using a transparent, conductive indium zinc oxide interlayer. The transparent, conductive oxide (TCO) layer provides excellent optical transmission as well as electrical conduction, suggesting suitability for Si/III-V hybrid devices including Si-based tandem solar cells. For bonding temperatures ranging from 100$^{circ}$C to 350$^{circ}$C, Ohmic behavior is observed in the sample stacks, with specific contact resistivity below 1 $Omega$cm$^2$ for samples bonded at 200$^{circ}$C. Optical absorption measurements show minimal parasitic light absorption, which is limited by the III-V interlayers necessary for Ohmic contact formation to TCOs. These results are promising for Ga$_{0.5}$In$_{0.5}$P/Si tandem solar cells operating at one sun or low concentration conditions.
Log in to be able to interact and post comments
comments
Fetching comments
Sign in to be able to follow your search criteria
