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Register a new user100 GHz Transistors from Wafer Scale Epitaxial Graphene
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High-performance graphene field-effect transistors have been fabricated on epitaxial graphene synthesized on a two-inch SiC wafer, achieving a cutoff frequency of 100 GHz for a gate length of 240 nm. The high-frequency performance of these epitaxial graphene transistors not only shows the highest speed for any graphene devices up to date, but it also exceeds that of Si MOSFETs at the same gate length. The result confirms the high potential of graphene for advanced electronics applications, marking an important milestone for carbon electronics.
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We report the realization of top-gated graphene nanoribbon field effect transistors (GNRFETs) of ~10 nm width on large-area epitaxial graphene exhibiting the opening of a band gap of ~0.14 eV. Contrary to prior observations of disordered transport and severe edge-roughness effects of GNRs, the experimental results presented here clearly show that the transport mechanism in carefully fabricated GNRFETs is conventional band-transport at room temperature, and inter-band tunneling at low temperature. The entire space of temperature, size, and geometry dependent transport properties and electrostatics of the GNRFETs are explained by a conventional thermionic emission and tunneling current model. Our combined experimental and modeling work proves that carefully fabricated narrow GNRs behave as conventional semiconductors, and remain potential candidates for electronic switching devices.
Up to two layers of epitaxial graphene have been grown on the Si-face of two-inch SiC wafers exhibiting room-temperature Hall mobilities up to 1800 cm^2/Vs, measured from ungated, large, 160 micron x 200 micron Hall bars, and up to 4000 cm^2/Vs, from top-gated, small, 1 micron x 1.5 micron Hall bars. The growth process involved a combination of a cleaning step of the SiC in a Si-containing gas, followed by an annealing step in Argon for epitaxial graphene formation. The structure and morphology of this graphene has been characterized using AFM, HRTEM, and Raman spectroscopy. Furthermore, top-gated radio frequency field effect transistors (RF-FETs) with a peak cutoff frequency fT of 100 GHz for a gate length of 240 nm were fabricated using epitaxial graphene grown on the Si face of SiC that exhibited Hall mobilities up to 1450 cm^2/Vs from ungated Hall bars and 1575 cm^2/Vs from top-gated ones. This is by far the highest cut-off frequency measured from any kind of graphene.
Control of the position and density of semiconductor quantum dots (QDs) is vital for a variety of emergent technologies, such as quantum photonics and advanced opto-electronic devices. However, established ordering methods typically call for ex-situ processing prior to growth that have a deleterious impact on the optical quality of nanostructures. Here, we apply a conventional epitaxial growth method - molecular beam epitaxy (MBE) - to achieve wafer scale positioning of optically active QDs with high reproducibility, tunable periodicity, and controlled density across an entire unpatterned 3-inch semiconductor wafer. Hereby, we exploit material thickness gradients across the wafer to modulate the QD nucleation probability and demonstrate how our approaches can be used to achieve strong periodic modulation of the local dot density tunable over length scales ranging from a few millimeters to at least a few hundred microns in one or two spatial directions. The methods are universal and are applicable to a wide variety of semiconductor material systems.
The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphene nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing.
This paper describes the behavior of top gated transistors fabricated using carbon, particularly epitaxial graphene on SiC, as the active material. In the past decade research has identified carbon-based electronics as a possible alternative to silicon-based electronics. This enthusiasm was spurred by high carbon nanotube carrier mobilities. However, nanotube production, placement, and control are all serious issues. Graphene, a thin sheet of graphitic carbon, can overcome some of these problems and therefore is a promising new electronic material. Although graphene devices have been built before, in this work we provide the first demonstration and systematic evaluation of arrays of a large number of transistors entirely produced using standard microelectronics methods. Graphene devices presented feature high-k dielectric, mobilities up to 5000 cm2/Vs and, Ion/Ioff ratios of up to 7, and are methodically analyzed to provide insight into the substrate properties. Typical of graphene, these micron-scale devices have negligible band gaps and therefore large leakage currents.
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