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Register a new userDevelopment of FTK architecture: a fast hardware track trigger for the ATLAS detector
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A. Annovi
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The Fast Tracker (FTK) is a proposed upgrade to the ATLAS trigger system that will operate at full Level-1 output rates and provide high quality tracks reconstructed over the entire detector by the start of processing in Level-2. FTK solves the combinatorial challenge inherent to tracking by exploiting the massive parallelism of Associative Memories (AM) that can compare inner detector hits to millions of pre-calculated patterns simultaneously. The tracking problem within matched patterns is further simplified by using pre-computed linearized fitting constants and leveraging fast DSPs in modern commercial FPGAs. Overall, FTK is able to compute the helix parameters for all tracks in an event and apply quality cuts in approximately one millisecond. By employing a pipelined architecture, FTK is able to continuously operate at Level-1 rates without deadtime. The system design is defined and studied using ATLAS full simulation. Reconstruction quality is evaluated for single muon events with zero pileup, as well as WH events at the LHC design luminosity. FTK results are compared with the tracking capability of an offline algorithm.
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Single muon triggers are crucial for the physics programmes at hadron collider experiments. To be sensitive to electroweak processes, single muon triggers with transverse momentum thresholds down to 20 GeV and dimuon triggers with even lower thresholds are required. In order to keep the rates of these triggers at an acceptable level these triggers have to be highly selective, i.e. they must have small accidental trigger rates and sharp trigger turn-on curves. The muon systems of the LHC experiments and experiments at future colliders like FCC-hh will use two muon chamber systems for the muon trigger, fast trigger chambers like RPCs with coarse spatial resolution and much slower precision chambers like drift-tube chambers with high spatial resolution. The data of the trigger chambers are used to identify the bunch crossing in which the muon was created and for a rough momentum measurement while the precise measurements of the muon trajectory by the precision chambers are ideal for an accurate muon momentum measurement. A compact muon track finding algorithm is presented, where muon track candidates are reconstructed using a binning algorithm based on a 1D Hough Transform. The algorithm has been designed and implemented on a System-On-Chip device. A hardware demonstration using Xilinx Evaluation boards ZC706 has been set-up to prove the concept. The system has demonstrated the feasibility to reconstruct muon tracks with a good angular resolution, whilst satisfying latency constraints. The demonstrated track-reconstruction system, the chosen architecture, the achievements to date and future options for such a system will be discussed.
The first stage of the ATLAS Fast TracKer (FTK) is an ATCA-based input interface system, where hits from the entire silicon tracker are clustered and organized into overlapping eta-phi trigger towers before being sent to the tracking engines. First, FTK Input Mezzanine cards receive hit data and perform clustering to reduce data volume. Then, the ATCA-based Data Formatter system will organize the trigger tower data, sharing data among boards over full mesh backplanes and optic fibers. The board and system level design concepts and implementation details, as well as the operation experiences from the FTK full-chain testing, will be presented.
The innermost part of the ATLAS experiment will be a pixel detector containing around 1750 individual detector modules. A detector control system (DCS) is required to handle thousands of I/O channels with varying characteristics. The main building blocks of the pixel DCS are the cooling system, the power supplies and the thermal interlock system, responsible for the ultimate safety of the pixel sensors. The ATLAS Embedded Local Monitor Board (ELMB), a multi purpose front end I/O system with a CAN interface, is foreseen for several monitoring and control tasks. The Supervisory, Control And Data Acquisition (SCADA) system will use PVSS, a commercial software product chosen for the CERN LHC experiments. We report on the status of the different building blocks of the ATLAS pixel DCS.
This proceedings describes the XFT stereo upgrade for the CDF Level 2 trigger system. Starting with the stereo finder boards, up to the XFT stereo track algorithim implementation in the Level 2 PC. This proceedings will discuss the effectiveness of the Level 2 Stereo track algorithm at achieving reduced trigger rates with high efficiencies during high luminosity running.
The High-Luminosity LHC (HL-LHC) will provide the unique opportunity to explore the nature of physics beyond the Standard Model of strong and electroweak interactions. Highly selective first-level triggers are essential for the physics programme of the ATLAS experiment at HL-LHC, where the instantaneous luminosity will exceed the instantaneous LHC Run 1 luminosity by about an order of magnitude. The ATLAS first-level muon trigger rate is dominated by low momentum muons, which are accepted because of the moderate momentum resolution of the RPC and TGC trigger chambers. This limitation can be overcome by exploiting the data of the precision Muon Drift-Tube (MDT) chambers in the first-level trigger decision. This requires continuous fast transfer of the MDT hits to the off-detector trigger logic and fast track reconstruction algorithms. The reduction of the muon trigger rate achievable with the proposed new trigger concept, the performance of a novel fast track reconstruction algorithm, and the first hardware demonstration of the scheme with muon testbeam data taken at the CERN Gamma Irradiation Facility are discussed.
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