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Register a new userTesting Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
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EDA Publishing Association
Publication date
2007
fields
Informatics Engineering
and research's language is
English
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In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-a-chip (SoC) environments. The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the adoption of the P1500 standard), the possibility to run the test at-speed, the reduced test time, and the good diagnostic capabilities. The paper reports figures about the achieved fault coverage, the required area overhead, and the performance slowdown, and compares the figures with those for alternative approaches, such as those based on full scan and sequential ATPG.
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This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.
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In this work, a novel quaternary algebra has been proposed that can be used to implement an arbitrary quaternary logic function in more than one systematic ways. The proposed logic has evolved from and is closely related to the Boolean algebra for binary domain; yet it does not lack the benefits of a higher-radix system. It offers seamless integration of the binary logic functions and expressions through a set of transforms and allows any binary logic simplification technique to be applied in quaternary domain. Since physical realization of the operators defined in this logic has recently been reported, it has become very important to have a well-defined algebra that will facilitate the algebraic manipulation of the novel quaternary logic and aid in designing various complex logic circuits. Therefore, based on our earlier works, here we describe the complete algebraic representation of this logic for the first time. The efficacy of the logic has been shown by designing and comparing several common logic circuits with existing designs in both binary and quaternary domain.
Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers new memory designs for executing tasks not traditionally associated with memories. A practical 3D-stacked memory is Hybrid Memory Cube (HMC), which provides significant access bandwidth and low power consumption in a small area. Although several studies have taken advantage of the novel architecture of HMC, its characteristics in terms of latency and bandwidth or their correlation with temperature and power consumption have not been fully explored. This paper is the first, to the best of our knowledge, to characterize the thermal behavior of HMC in a real environment using the AC-510 accelerator and to identify temperature as a new limitation for this state-of-the-art design space. Moreover, besides bandwidth studies, we deconstruct factors that contribute to latency and reveal their sources for high- and low-load accesses. The results of this paper demonstrates essential behaviors and performance bottlenecks for future explorations of packet-switched and 3D-stacked memories.
Use case scenarios are created during the analysis phase to specify software system requirements and can also be used for creating system level test cases. Using use cases to get system tests has several benefits including test design at early stages of software development life cycle that reduces over all development cost of the system. Current approaches for system testing using use cases involve functional details and does not include guards as passing criteria i.e. use of class diagram that seem to be difficult at very initial level which lead the need of specification based testing without involving functional details. In this paper, we proposed a technique for system testing directly derived from the specification without involving functional details. We utilize initial and post conditions applied as guards at each level of the use cases that enables us generation of formalized test cases and makes it possible to generate test cases for each flow of the system. We used use case scenarios to generate system level test cases, whereas system sequence diagram is being used to bridge the gap between the test objective and test cases, derived from the specification of the system. Since, a state chart derived from the combination of sequence diagrams can model the entire behavior of the system.Generated test cases can be employed and executed to state chart in order to capture behavior of the system with the state change.All these steps enable us to systematically refine the specification to achieve the goals of system testing at early development stages.
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