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تسجيل مستخدم جديدMolecular Polar Belief Propagation Decoder and Successive Cancellation Decoder
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Zhiwei Zhong
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By constructing chemical reaction networks (CRNs), this paper proposes a method of synthesizing polar decoder using belief propagation (BP) algorithm and successive cancellation (SC) algorithm, respectively. Theoretical analysis and simulation results have validated the feasibility of the method. Reactions in the proposed design could be experimentally implemented with DNA strand displacement reactions, making the proposed polar decoders promising for wide application in nanoscale devices.
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Polar codes, discovered by Ar{i}kan, are the first error-correcting codes with an explicit construction to provably achieve channel capacity, asymptotically. However, their error-correction performance at finite lengths tends to be lower than existin
g capacity-approaching schemes. Using the successive-cancellation algorithm, polar decoders can be designed for very long codes, with low hardware complexity, leveraging the regular structure of such codes. We present an architecture and an implementation of a scalable hardware decoder based on this algorithm. This design is shown to scale to code lengths of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by the amount of available SRAM.
This paper presents a hardware architecture of fast simplified successive cancellation (fast-SSC) algorithm for polar codes, which significantly reduces the decoding latency and dramatically increases the throughput. Algorithmically, fast-SSC algorit
hm suffers from the fact that its decoder scheduling and the consequent architecture depends on the code rate; this is a challenge for rate-compatible system. However, by exploiting the homogeneousness between the decoding processes of fast constituent polar codes and regular polar codes, the presented design is compatible with any rate. The scheduling plan and the intendedly designed process core are also described. Results show that, compared with the state-of-art decoder, proposed design can achieve at least 60% latency reduction for the codes with length N = 1024. By using Nangate FreePDK 45nm process, proposed design can reach throughput up to 5.81 Gbps and 2.01 Gbps for (1024, 870) and (1024, 512) polar code, respectively.
This paper presents an efficient hardware design approach for list successive cancellation (LSC) decoding of polar codes. By applying path-overlapping scheme, the l instances of (l > 1) successive cancellation (SC) decoder for LSC with list size l ca
n be cut down to only one. This results in a dramatic reduction of the hardware complexity without any decoding performance loss. We also develop novel approaches to reduce the latencyassociated with the pipeline scheme. Simulation results show that with proposed design approach the hardware efficiency is increased significantly over the recently proposed LSC decoders.
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