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تسجيل مستخدم جديدDevelopment of active edge pixel sensors and four-side buttable modules using vertical integration technologies
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We present an R&D activity focused on the development of novel modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The modules consist of n-in-p pixel sensors, 100 or 200 $mu$m thick, produced at VTT (Finland) with an active edge technology, which considerably reduces the dead area at the periphery of the device. The sensors are interconnected with solder bump-bonding to the ATLAS FE-I3 and FE-I4 read-out chips, and characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements will be discussed for devices before and after irradiation up to a fluence of $5times 10^{15}$ eqcm. We will also report on the R&D activity to obtain Inter Chip Vias (ICVs) on the ATLAS read-out chip in collaboration with the Fraunhofer Institute EMFT. This step is meant to prove the feasibility of the signal transport to the newly created readout pads on the backside of the chips allowing for four side buttable devices without the presently used cantilever for wire bonding. The read-out chips with ICVs will be interconnected to thin pixel sensors, 75 $mu$m and 150 $mu$m thick, with the Solid Liquid Interdiffusion (SLID) technology, which is an alternative to the standard solder bump-bonding.
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To cope with the High Luminosity LHC harsh conditions, the ATLAS inner tracker has to be upgraded to meet requirements in terms of radiation hardness, pile up and geometrical acceptance. The active edge technology allows to reduce the insensitive are
a at the border of the sensor thanks to an ion etched trench which avoids the crystal damage produced by the standard mechanical dicing process. Thin planar n-on-p pixel sensors with active edge have been designed and produced by LPNHE and FBK foundry. Two detector module prototypes, consisting of pixel sensors connected to FE-I4B readout chips, have been tested with beams at CERN and DESY. In this paper the performance of these modules are reported. In particular the lateral extension of the detection volume, beyond the pixel region, is investigated and the results show high hit-efficiency also at the detector edge, even in presence of guard rings.
Silicon pixel modules employing n-in-p planar sensors with an active thickness of 200 $mu$m, produced at CiS, and 100-200 $mu$m thin active/slim edge sensor devices, produced at VTT in Finland have been interconnected to ATLAS FE-I3 and FE-I4 read-ou
t chips. The thin sensors are designed for high energy physics collider experiments to ensure radiation hardness at high fluences. Moreover, the active edge technology of the VTT production maximizes the sensitive region of the assembly, allowing for a reduced overlap of the modules in the pixel layer close to the beam pipe. The CiS production includes also four chip sensors according to the module geometry planned for the outer layers of the upgraded ATLAS pixel detector to be operated at the HL-LHC. The modules have been characterized using radioactive sources in the laboratory and with high precision measurements at beam tests to investigate the hit efficiency and charge collection properties at different bias voltages and particle incidence angles. The performance of the different sensor thicknesses and edge designs are compared before and after irradiation up to a fluence of $1.4times10^{16}n_{eq}/cm^{2}$.
We present the results of the characterization of pixel modules composed of 75 um thick n-in-p sensors and ATLAS FE-I3 chips, interconnected with the SLID (Solid Liquid Inter-Diffusion) technology. This technique, developed at Fraunhofer-EMFT, is exp
lored as an alternative to the bump-bonding process. These modules have been designed to demonstrate the feasibility of a very compact detector to be employed in the future ATLAS pixel upgrades, making use of vertical integration technologies. This module concept also envisages Inter-Chip-Vias (ICV) to extract the signals from the backside of the chips, thereby achieving a higher fraction of active area with respect to the present pixel module design. In the case of the demonstrator module, ICVs are etched over the original wire bonding pads of the FE-I3 chip. In the modules with ICVs the FE-I3 chips will be thinned down to 50 um. The status of the ICV preparation is presented.
The R&D activity presented is focused on the development of new modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The performance after irradiation of n-in-p pixel sensors of different active thicknesses is studie
d, together with an investigation of a novel interconnection technique offered by the Fraunhofer Institute EMFT in Munich, the Solid-Liquid-InterDiffusion (SLID), which is an alternative to the standard solder bump-bonding. The pixel modules are based on thin n-in-p sensors, with an active thickness of 75 um or 150 um, produced at the MPI Semiconductor Laboratory (MPI HLL) and on 100 um thick sensors with active edges, fabricated at VTT, Finland. Hit efficiencies are derived from beam test data for thin devices irradiated up to a fluence of 4e15 neq/cm^2. For the active edge devices, the charge collection properties of the edge pixels before irradiation is discussed in detail, with respect to the inner ones, using measurements with radioactive sources. Beyond the active edge sensors, an additional ingredient needed to design four side buttable modules is the possibility of moving the wire bonding area from the chip surface facing the sensor to the backside, avoiding the implementation of the cantilever extruding beyond the sensor area. The feasibility of this process is under investigation with the FE-I3 SLID modules, where Inter Chip Vias are etched, employing an EMFT technology, with a cross section of 3 um x 10 um, at the positions of the original wire bonding pads.
CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel
pitch ($sim 20 mu m$) and low material budget ($sim 0.2-0.3% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity epitaxial layers leads to the better radiation hardness and allows the implementation of accelerated readout circuits. The TowerJazz $0.18 mu m$ CMOS process being one of the most relevant examples recently became of interest for several future detector projects. The most imminent of these project is an upgrade of the Inner Tracking System (ITS) of the ALICE detector at LHC. It will be followed by the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. Other experiments like ILD consider CPS as one of the viable options for flavour tagging and tracking sub-systems.
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