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تسجيل مستخدم جديدAt-Speed Logic BIST for IP Cores
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نشر من قبل
EDA Publishing Association
تاريخ النشر
2007
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الهندسة المعلوماتية
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English
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This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.
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