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In this work, we briefly overview various options for Josephson junctions which should be scalable down to nanometer range for utilization in nanoscale digital superconducting technology. Such junctions should possess high values of critical current, $I_c$, and normal state resistance, $R_n$. Another requirement is the high reproducibility of the junction parameters across a wafer in a fabrication process. We argue that Superconductor - Normal metal - Superconductor (SN-N-NS) Josephson junction of variable thickness bridge geometry is a promising choice to meet these requirements. Theoretical analysis of SN-N-NS junction is performed in the case where the distance between the S-electrodes is comparable to the coherence length of the N-material. The restriction on the junction geometrical parameters providing the existence of superconductivity in the S-electrodes is derived for the current flowing through the junction of an order of $I_c$. The junction heating, as well as available mechanisms for the heat removal, is analyzed. The obtained results show that an SN-N-NS junction with a high (sub-millivolt) value of $I_cR_n$ product can be fabricated from a broadly utilized combination of materials like Nb/Cu using well-established technological processes. The junction area can be scaled down to that of semiconductor transistors fabricated in the frame of a 40-nm process.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with $T_1$ relaxation times averaging above 50$~mu$s ($Q>$1.5$times$ 10$^6$). Current shadow-evaporation techniques for aluminum-based
Magnetic flux quantization in superconductors allows the implementation of fast and energy-efficient digital superconducting circuits. However, the information representation in magnetic flux severely limits their functional density presenting a long
A novel way to realize a pi Josephson junction is proposed, based on a weak link in an unconventional d-wave superconductor with appropriately chosen boundary geometry. The critical current of such a junction is calculated from a fully selfconsistent
Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing tec
New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stoplayers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (Ic) targeting