We report a complementary metal oxide semiconductor (CMOS) technology compatible ferroelectric tunnel junction memristor grown directly on top of a Silicon substrate using a scandium doped aluminum nitride as the ferroelectric layer.
In 1963, Moll and Tarui suggested that the field-effect conductance of a semiconductor could be controlled by the remanent polarization of a ferroelectric (FE) material to create a ferroelectric field-effect transistor (FE-FET). However, subsequent e
fforts to produce a practical, compact FE-FET have been plagued by low retention and incompatibility with Complementary Metal Oxide Semiconductor (CMOS) process integration. These difficulties led to the development of trapped-charge based memory devices (also called floating gate or flash memory), and these are now the mainstream non-volatile memory (NVM) technology. Over the past two decades, advances in oxide FE materials have rejuvenated the field of ferroelectrics and made FE random access memories (FE-RAM) a commercial reality. Despite these advances, commercial FE-RAM based on lead zirconium titanate (PZT) has stalled at the 130 nm due to process challenges.The recent discovery of scandium doped aluminum nitride (AlScN) as a CMOS compatible ferroelectric presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approx. 350 C). This temperature is compatible with CMOS back end of line processes. Here, we present a FE-FET device composed of an AlScN FE dielectric layer integrated with a channel layer of a van der Waals two-dimensional (2D) semiconductor, MoS2. Our devices show an ON/OFF ratio ~ 10^6, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable, two-state memory retention for up to 10^4 seconds. Our simulations and experimental results suggest that the combination of AlScN and 2D semiconductors is nearly ideal for low power FE-FET memory. These results demonstrate a new approach in embedded memory and in-memory computing, and could even lead to effective neuromorphic computing architectures.
The magnetic tunnel junction is a cornerstone of spintronic devices and circuits, providing the main way to convert between magnetic and electrical information. In state-of-the-art magnetic tunnel junctions, magnesium oxide is used as the tunnel barr
ier between magnetic electrodes, providing a uniquely large tunnel magnetoresistance at room temperature. However, the wide bandgap and band alignment of magnesium oxide-iron systems increases the resistance-area product and causes challenges of device-to-device variability and tunnel barrier degradation under high current. Here, we study using first principles narrower-bandgap scandium nitride tunneling properties and transport in magnetic tunnel junctions in comparison to magnesium oxide. These simulations demonstrate a high tunnel magnetoresistance in Fe/ScN/Fe MTJs via {Delta}_1 and {Delta}_2 symmetry filtering with low wavefunction decay rates, allowing a low resistance-area product. The results show that scandium nitride could be a new tunnel barrier material for magnetic tunnel junction devices to overcome variability and current-injection challenges.
Memristors are continuously tunable resistors that emulate synapses. Conceptualized in the 1970s, they traditionally operate by voltage-induced displacements of matter, but the mechanism remains controversial. Purely electronic memristors have recent
ly emerged based on well-established physical phenomena with albeit modest resistance changes. Here we demonstrate that voltage-controlled domain configurations in ferroelectric tunnel barriers yield memristive behaviour with resistance variations exceeding two orders of magnitude and a 10 ns operation speed. Using models of ferroelectric-domain nucleation and growth we explain the quasi-continuous resistance variations and derive a simple analytical expression for the memristive effect. Our results suggest new opportunities for ferroelectrics as the hardware basis of future neuromorphic computational architectures.
The possibility of reconciliation between seemingly mutually exclusive properties in one system can not only lead to theoretical breakthroughs but also potential novel applications. The research on the coexistence of two purportedly contra-indicated
properties, ferroelectricity/polarity and conductivity, proposed by Anderson and Blount over 50 years ago was recently revitalized by the discovery of the first unambiguous polar metal LiOsO3 and further fueled by the demonstration of the first switchable ferroelectric metal WTe2. In this review, we first discuss the reasons why the coexistence of ferroelectricity/polarity and conductivity have been deemed incompatible, followed by a review on the history of ferroelectric/polar metals. Secondly, we review the important milestones along with the corresponding mechanisms for the ferroelectric/polar metallic phases in these materials. Thirdly, we summarize the design approaches for ferroelectric/polar metals. Finally, we discuss the future prospects and potential applications of ferroelectric/polar metals.
We propose energy band engineering to enhance tunneling electroresistance (TER) in ferroelectric tunnel junctions (FTJs). We predict that an ultrathin dielectric layer with a smaller band gap, embedded into a ferroelectric barrier layer, acts as a sw
itch controlling high and low conductance states of an FTJ depending on polarization orientation. Using first-principles modeling based on density functional theory, we investigate this phenomenon for a prototypical SrRuO3/BaTiO3/SrRuO3 FTJ with a BaSnO3 monolayer embedded in the BaTiO3 barrier. We show that in such a composite-barrier FTJ, ferroelectric polarization of BaTiO3 shifts the conduction band minimum of the BaSnO3 monolayer above or below the Fermi energy depending on polarization orientation. The resulting switching between direct and resonant tunneling leads to a TER effect with a giant ON/OFF conductance ratio. The proposed resonant band engineering of FTJs can serve as a viable tool to enhance their performance useful for device application.