اشترك بالحزمة الذهبية واحصل على وصول غير محدود شمرا أكاديميا
تسجيل مستخدم جديدFast and effective techniques for T-count reduction via spider nest identities
65
0
0.0
(
0
)
اسأل ChatGPT حول البحث
ﻻ يوجد ملخص باللغة العربية
In fault-tolerant quantum computing systems, realising (approximately) universal quantum computation is usually described in terms of realising Clifford+T operations, which is to say a circuit of CNOT, Hadamard, and $pi/2$-phase rotations, together with T operations ($pi/4$-phase rotations). For many error correcting codes, fault-tolerant realisations of Clifford operations are significantly less resource-intensive than those of T gates, which motivates finding ways to realise the same transformation involving T-count (the number of T gates involved) which is as low as possible. Investigations into this problem [arXiv:1206.0758, 1303.2042, 1308.4134, 1601.07363, 1606.01904, 1701.00140] has led to observations that this problem is closely related to NP-hard tensor decomposition problems [arXiv:1712.01557] and is tantamount to the difficult problem of decoding exponentially long Reed-Muller codes [arXiv:1601.07363]. This problem then presents itself as one for which must be content in practise with approximate optimisation, in which one develops an array of tactics to be deployed through some pragmatic strategy. In this vein, we describe techniques to reduce the T-count, based on the effective application of spider nest identities: easily recognised products of parity-phase operations which are equivalent to the identity operation. We demonstrate the effectiveness of such techniques by obtaining improvements in the T-counts of a number of circuits, in run-times which are typically less than the time required to make a fresh cup of coffee.
قيم البحث
اقرأ أيضاً
In this paper we exploit the utility of the triangle symbol which has a complicated expression in terms of spider diagrams in ZX-calculus, and its role within the ZX-representation of AND-gates in particular. First, we derive spider nest identities w
hich are of key importance to recent developments in quantum circuit optimisation and T-count reduction in particular. Then, using the same rule set, we prove a completeness theorem for quantum Boolean circuits (QBCs) whose rewriting rules can be directly used for a new method of T-count reduction. We give an algorithm based on this method and show that the results of our algorithm outperform the results of all the previous best non-probabilistic algorithms.
Nested quantum annealing correction (NQAC) is an error correcting scheme for quantum annealing that allows for the encoding of a logical qubit into an arbitrarily large number of physical qubits. The encoding replaces each logical qubit by a complete
graph of degree $C$. The nesting level $C$ represents the distance of the error-correcting code and controls the amount of protection against thermal and control errors. Theoretical mean-field analyses and empirical data obtained with a D-Wave Two quantum annealer (supporting up to $512$ qubits) showed that NQAC has the potential to achieve a scalable effective temperature reduction, $T_{rm eff} sim C^{-eta}$, with $eta leq 2$. We confirm that this scaling is preserved when NQAC is tested on a D-Wave 2000Q device (supporting up to $2048$ qubits). In addition, we show that NQAC can be also used in sampling problems to lower the effective temperature of a quantum annealer. Such effective temperature reduction is relevant for machine-learning applications. Since we demonstrate that NQAC achieves error correction via an effective reduction of the temperature of the quantum annealing device, our results address the problem of the temperature scaling law for quantum annealers, which requires the temperature of quantum annealers to be reduced as problems of larger sizes are attempted to be solved.
Sketching uses randomized Hash functions for dimensionality reduction and acceleration. The existing sketching methods, such as count sketch (CS), tensor sketch (TS), and higher-order count sketch (HCS), either suffer from low accuracy or slow speed
in some tensor based applications. In this paper, the proposed fast count sketch (FCS) applies multiple shorter Hash functions based CS to the vector form of the input tensor, which is more accurate than TS since the spatial information of the input tensor can be preserved more sufficiently. When the input tensor admits CANDECOMP/PARAFAC decomposition (CPD), FCS can accelerate CS and HCS by using fast Fourier transform, which exhibits a computational complexity asymptotically identical to TS for low-order tensors. The effectiveness of FCS is validated by CPD, tensor regression network compression, and Kronecker product compression. Experimental results show its superior performance in terms of approximation accuracy and computational efficiency.
While mapping a quantum circuit to the physical layer one has to consider the numerous constraints imposed by the underlying hardware architecture. Connectivity of the physical qubits is one such constraint that restricts two-qubit operations such as
CNOT to connected qubits. SWAP gates can be used to place the logical qubits on admissible physical qubits, but they entail a significant increase in CNOT-count, considering the fact that each SWAP gate can be implemented by 3 CNOT gates. In this paper we consider the problem of reducing the CNOT-count in Clifford+T circuits on connectivity constrained architectures such as noisy intermediate-scale quantum (NISQ) (Preskill, 2018) computing devices. We slice the circuit at the position of Hadamard gates and build the intermediate portions. We investigated two kinds of partitioning - (i) a simple method of partitioning the gates of the input circuit based on the locality of H gates and (ii) a second method of partitioning the phase polynomial of the input circuit. The intermediate {CNOT,T} sub-circuits are synthesized using Steiner trees, significantly improving on the methods introduced by Nash, Gheorghiu, Mosca[2020] and Kissinger, de Griend[2019]. We compared the performance of our algorithms while mapping different benchmark circuits as well as random circuits to some popular architectures such as 9-qubit square grid, 16-qubit square grid, Rigetti 16-qubit Aspen, 16-qubit IBM QX5 and 20-qubit IBM Tokyo. We found that for both the benchmark and random circuits our first algorithm that uses the simple slicing technique dramatically reduces the CNOT-count compared to naively using SWAP gates. Our second slice-and-build algorithm also performs very well for benchmark circuits.
We present a constructive method to create quantum circuits that implement oracles $|xrangle|yrangle|0rangle^k mapsto |xrangle|y oplus f(x)rangle|0rangle^k$ for $n$-variable Boolean functions $f$ with low $T$-count. In our method $f$ is given as a 2-
regular Boolean logic network over the gate basis ${land, oplus, 1}$. Our construction leads to circuits with a $T$-count that is at most four times the number of AND nodes in the network. In addition, we propose a SAT-based method that allows us to trade qubits for $T$ gates, and explore the space/complexity trade-off of quantum circuits. Our constructive method suggests a new upper bound for the number of $T$ gates and ancilla qubits based on the multiplicative complexity $c_land(f)$ of the oracle function $f$, which is the minimum number of AND gates that is required to realize $f$ over the gate basis ${land, oplus, 1}$. There exists a quantum circuit computing $f$ with at most $4 c_land(f)$ $T$ gates using $k = c_land(f)$ ancillae. Results known for the multiplicative complexity of Boolean functions can be transferred. We verify our method by comparing it to different state-of-the-art compilers. Finally, we present our synthesis results for Boolean functions used in quantum cryptoanalysis.
سجل دخول لتتمكن من نشر تعليقات
التعليقات
جاري جلب التعليقات
سجل دخول لتتمكن من متابعة معايير البحث التي قمت باختيارها
