ترغب بنشر مسار تعليمي؟ اضغط هنا

Computing with volatile memristors: An application of non-pinched hysteresis

55   0   0.0 ( 0 )
 نشر من قبل Sergey Shevchenko N.
 تاريخ النشر 2016
والبحث باللغة English




اسأل ChatGPT حول البحث

The possibility of in-memory computing with volatile memristive devices, namely, memristors requiring a power source to sustain their memory, is demonstrated. We have adopted a hysteretic graphene-based field emission structure as a prototype of volatile memristor, which is characterized by a non-pinched hysteresis loop. Memristive model of the structure is developed and used to simulate a polymorphic circuit implementing in-memory computing gates such as the material implication. Specific regions of parameter space realizing useful logic functions are identified. Our results are applicable to other realizations of volatile memory devices.



قيم البحث

اقرأ أيضاً

69 - J. Kim , Y. V. Pershin , M. Yin 2019
It has been suggested that all resistive-switching memory cells are memristors. The latter are hypothetical, ideal devices whose resistance, as originally formulated, depends only on the net charge that traverses them. Recently, an unambiguous test h as been proposed [J. Phys. D: Appl. Phys. {bf 52}, 01LT01 (2019)] to determine whether a given physical system is indeed a memristor or not. Here, we experimentally apply such a test to both in-house fabricated Cu-SiO2 and commercially available electrochemical metallization cells. Our results unambiguously show that electrochemical metallization memory cells are not memristors. Since the particular resistance-switching memories employed in our study share similar features with many other memory cells, our findings refute the claim that all resistance-switching memories are memristors. They also cast doubts on the existence of ideal memristors as actual physical devices that can be fabricated experimentally. Our results then lead us to formulate two memristor impossibility conjectures regarding the impossibility of building a model of physical resistance-switching memories based on the memristor model.
This paper presents a novel resistive-only Binary and Ternary Content Addressable Memory (B/TCAM) cell that consists of two Complementary Resistive Switches (CRSs). The operation of such a cell relies on a logic$rightarrow$ON state transition that enables this novel CRS application.
A non-volatile SRAM cell is proposed for low power applications using Spin Transfer Torque-Magnetic Tunnel Junction (STT-MTJ) devices. This novel cell offers non-volatile storage, thus allowing selected blocks of SRAM to be switched off during standb y operation. To further increase the power savings, a write termination circuit is designed which detects completion of MTJ write and closes the bidirectional current path for the MTJ. A reduction of 25.81% in the number of transistors and a reduction of 2.95% in the power consumption is achieved in comparison to prior work on write termination circuits.
Modern computing systems are embracing non-volatile memory (NVM) to implement high-capacity and low-cost main memory. Elevated operating voltages of NVM accelerate the aging of CMOS transistors in the peripheral circuitry of each memory bank. Aggress ive device scaling increases power density and temperature, which further accelerates aging, challenging the reliable operation of NVM-based main memory. We propose HEBE, an architectural technique to mitigate the circuit aging-related problems of NVM-based main memory. HEBE is built on three contributions. First, we propose a new analytical model that can dynamically track the aging in the peripheral circuitry of each memory bank based on the banks utilization. Second, we develop an intelligent memory request scheduler that exploits this aging model at run time to de-stress the peripheral circuitry of a memory bank only when its aging exceeds a critical threshold. Third, we introduce an isolation transistor to decouple parts of a peripheral circuit operating at different voltages, allowing the decoupled logic blocks to undergo long-latency de-stress operations independently and off the critical path of memory read and write accesses, improving performance. We evaluate HEBE with workloads from the SPEC CPU2017 Benchmark suite. Our results show that HEBE significantly improves both performance and lifetime of NVM-based main memory.
In cloud and edge computing models, it is important that compute devices at the edge be as power efficient as possible. Long short-term memory (LSTM) neural networks have been widely used for natural language processing, time series prediction and ma ny other sequential data tasks. Thus, for these applications there is increasing need for low-power accelerators for LSTM model inference at the edge. In order to reduce power dissipation due to data transfers within inference devices, there has been significant interest in accelerating vector-matrix multiplication (VMM) operations using non-volatile memory (NVM) weight arrays. In NVM array-based hardware, reduced bit-widths also significantly increases the power efficiency. In this paper, we focus on the application of quantization-aware training algorithm to LSTM models, and the benefits these models bring in terms of resilience against both quantization error and analog device noise. We have shown that only 4-bit NVM weights and 4-bit ADC/DACs are needed to produce equivalent LSTM network performance as floating-point baseline. Reasonable levels of ADC quantization noise and weight noise can be naturally tolerated within our NVMbased quantized LSTM network. Benchmark analysis of our proposed LSTM accelerator for inference has shown at least 2.4x better computing efficiency and 40x higher area efficiency than traditional digital approaches (GPU, FPGA, and ASIC). Some other novel approaches based on NVM promise to deliver higher computing efficiency (up to 4.7x) but require larger arrays with potential higher error rates.
التعليقات
جاري جلب التعليقات جاري جلب التعليقات
سجل دخول لتتمكن من متابعة معايير البحث التي قمت باختيارها
mircosoft-partner

هل ترغب بارسال اشعارات عن اخر التحديثات في شمرا-اكاديميا